i'm pretty sure the line of thought was something like 1.75v would be the next voltage which won't compromise the stability of the system. you need to be careful when adjusting the CPU PLL voltage, as if there is also an adjustment called SB 1.5V or SB SATA 1.5V, this is the Southbridge PLL voltage and my experience with this is, keep its actual voltage and the CPU PLL actual voltage, at least 0.1v apart. Why you ask? BEcause if you don't the system will behave erratically at best, and at worst you will end up with a system that responds like it's hungover and get random usb device dropouts, gpu instability, and all other things of annoying problems that won't make the system unpostable but it will irritate you to no end.
I try and keep the SB 1.5V PLL lower than 1.70v because on both X48 and P45s i've manually set this on this was about the highest I could go before it began to introduce instability and erratic behaviour. CPU PLL on the other hand I prefer to keep that higher as it can tolerate 1.8-1.9v with a big smile and open arms. 1.60v SB 1.5V, and either 1.52v CPU PPL or 1.70+V CPU PLL.
Try the 1.75V setting it won't damage the CPU if thats what you are worried about. I've run 1.9V on my Asus Rampage Formula for a good week or more, but in the end i Reduced it down to 1.78v or so because there was no benefit from such a high value as even it couldn't fix the inherent vrm phase limitations of the FSB with a quad core. At best it gave me a little more stability, but not enough to prevent full system locks completely. It probably gave me an extra 5-10mins before a hard freeze would set in while running Prime95 or Linpack. This was with 495MHz FSB.
Edit:
I used all my strength and with one hard pull that finger of mine came out, and low and behold I bothered opening up the ICH9R datasheet thats been sitting on my system for months.
So unless the SB 1.5V has more than one adjustment setting, it's more than likely that this voltage setting is a common input voltage to supply all the individual PLL circuits for each source that requires a clock reference.
Without further adue, heres the list of all the PLLs we break or fix by adjusting the SB 1.5V setting on any board sporting a ICH9/10 sb, and courtesy of Intel a generic explanation of each for reference.
VccDMIPLL - 1.5 V supply for core well logic. This signal is used for the DMI PLL. This power may be shut off in S3, S4, S5 or G3 states.
VccSATAPLL - 1.5 V supply for core well logic. This signal is used for the SATA PLL. This power may be shut off in S3, S4, S5 or G3 states. Must be powered even if SATA is not used.
VccGLANPLL - 1.5 V supply for core well logic. This signal is used for the integrated Gigabit LAN PLL. This power is shut off in S3, S4, S5 and G3 states.
VccUSBPLL - 1.5 V supply for core well logic. This signal is used for the USB PLL. This power may be shut off in S3, S4, S5 or G3 states. Must be powered even if USB not used.
After brief realization, a single input voltage to supply all the PLLs on the SB explains the broad range of irritations and problems i can replicate with precision just by accidentally or purposely setting the CPU PLL and SB PLL voltages no less than 0.06-0.07v of each other. The closer you go the worse the onset of the problems, the most annoying but harmless problem is when my USB keyboard becomes the victim of this scenario, and I really need to change settings in the bios but low and behold keys either don't do anything or fall into a repetition loop until you manage to navigate your way through the bios by luck or that the next post you go into the bios you just might be lucky enough that the PLL crosstalking affects something other than your key to fixing the problem
The key to a stable system is destabilizing it and then working out what you actually destabilized, why it impacted half of your system and not the other, then making adjustments if possible to isolate that voltage from any nearby input voltages. Sometimes a distance of 0.01-0.02v is adequate, but with PLL supply inputs a safe buffer would be at least 0.08-0.1v from another other PLL supply voltages used for internal phase deskewing. The only reason I can think of that would satisfy the solution is that the voltage regulation circuitry supplies both traces from a common down-transformed supply. This would account for why the jitter becomes so heavy as those pll supply voltages get nearer to either ones set voltage, and why that jitter exhibits cross talk as the gap drops below 0.05v.
The jitter at the output buffer is most likely the result of the voltage ringing back along the traces length to its source, and the other pll voltage being such a close voltage the ringing / jitter decides "hey, look over there thats our ticket to freedom! that nasty receiver waiting for us will never expect us to switch traces" and before you know it the receiver on the output side is unable to do its job (which happens to be ringback draining) and that small gap in voltage for either supply effectively adds a point for the ringback to easily cross the traces and pollute the other PLL supply since the ringing is always a result of the input side grounding the signal and is usually harmless when it rings towards the output supply, and there will be receivers to handle the filtering of the voltage ring back in most cases. There is no need for these on the input side, and that's why the ringing towards the input turns harmless jitter into super bad ass evil jitter, and no super bad ass evil jitter battling super hero to save the input supply buffer from its path of chaos!
Since not overclocking is hardly a viable option for enthusiast motherboard market that loves overclocking, we are paying the price of overclocking freedom in the premium jump in price for the expensive 6+ layer pcbs our high end boards are generously endowed with. And they say overclocking is all about getting more value from cheaper value parts, while being true with respect to components which we purchase seperately such as the cpu or gpu, it's now becoming offset by the continously rising premiums we are forced to pay for a board. What we save on cheaper hardware components, we are shifting to the motherboard companies so we can justify the satisfaction of a $200 part performing like a $500 one, even though we paid an extra $200 for a board specially designed to eliminate the problems we created when we went outside the design specs of the architecture.
I personally don't mind copping that steep premium if it means the board I'm paying 2-3 times more for has more than adequate overkill designed into it, as long as the engineers designing it are competent enough that the boards design both behaves like the spec requires, and beyond those limits at least tries to work like originally intended to. I'm seeing lots of boards that clock high but don't behave the way they should, this makes for unpleasant overclocking and unexpected behaviour we shouldn't be coming across because it occured simply as a result of taking shortcuts or adding features that double up as trip wires to undocumented flaws. Which were probably not documented because the engineers who designed it originally took a different approach to avoid such a scenario. I don't want to call names so I won't but there are far and few between boards designed to work flawlessly with the architecture its based on, and the rest of the boards which spit the dummy when two settings conflict with each other, and give no end of problems or solutions.
Reply With Quote
Bookmarks