Quote Originally Posted by Lightman View Post
No it's not and Particle is more or less right.
B3 fix for TBL errata was a bypass. It didn't fix originally planned functionality. The fix brings minimal performance penalty, because TLB is flushed every time there can be some dirty data in it. I think Anand was doing more in-depth analysis.
If you mean this?

http://www.nordichardware.com/news,7189.html
or this?
http://www.xbitlabs.com/articles/cpu...m-x4-9850.html

Unfortunately, AMD engineers didn’t really explain to us what was done specifically to fix the TLB bug in the new B3 processor stepping. However, some indirect data we have at our disposal gives us reason to believe that now, after the processor core changes the bit flags for page table entries stored in L2 cache, they are all evicted into L3 cache. This may be the reason fore the latency to get a little bit higher.