Deneb Samples are almost out

[Calmatory]

Cache increases and comparison against Core architecture are more than useless really. Why? Because another architecture has IMC and another one does not. Besides, cache misses are unique to both architectures and increasing cache size to compensate and reduce the miss is different for both architectures. Yes, some guesstimations can be made, but they shouldn't be considered very valid unless otherwise proven in practice.

It also depends what kind of cache misses they are. E.g. instruction cache miss is more vital than data cache miss.