gah tRD phase pull-ins are evil stuff. though I did manage to figure out something useful before I corrupted half my registry and wasted my night repairing my vista install!
for delayed dram clk skews, phase pull-ins on a/b1-> increment the dimm1/2/3/4 fine clock delay, and delay decrements it.
for advanced dram clk skews, phase pull-ins on a/b1-> increment the dimm1/2/3/4 fine clock delay, and advance increments it.
50ps seems to be equivalent to -+1t.
if all 4 dimm fine clock delay are not aligned, no read delay phase adjust clocks are added, if there is correct alignment then by pulling in phases the read delay phase adjust clocks are incremented, and mch data strobe is advance skewed with respect to DRAM data strobe.
you can use a phase pull-ins along with dram clk skews to adjust the dimm fine clock delay, but they are damned touchy and more likely you'll corrupt the cmos or your OS if you arent careful! so not for the weak at heart.
in a few days once I run my system through a bunch of tests to get 480-485fsb stable 24/7 properly, i'll work out exactly what the result of pulling in specific phases has in regards to data strobe skewing values. this time i wont be trying it with common pl of 7 at 486fsb on 333mhz strap, i'll be sticking to something like performance level of 8 or 9 since neither are too tight on this strap.
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