Originally Posted by
mikeyakame
gtl 0 is for the address clock strobe input reference voltage for die 0
gtl 1 is for the data clock strobe input reference voltage for die 0
a quad core has gtl 2 and gtl 3, which are die 1 reference inputs for address and data strobes respectively.
I personally don't know why Asus offset the two values. I have a few alternate ideas for the reason behind it, but just guesses if anything.
address strobe occurs on low clock, while data strobe occurs on high clock.
i dont know how right this theory is so don't take it as more than a stab in the dark at an explanation that just crossed my mind that made a bit of sense as to why.
lower gtlref for 0 increases ringback margin on the supply voltage for the address strobe, moving the logical 0 clock valid window lower. higher gtlref for 1 increases ringback margin on the supply voltage for the data strobe, moving the logical 1 clock valid window higher. if you overlaid both waves on top of each other then the input reference voltage for each would be more tolerable to ringback on the line as the fsb frequency is adjusted outside the tuned band of frequencies, so that the common denominator of overclockers (people who change settings according to what others use) without an extensive knowledge of electronics design have more freedom to increase clocks without risking data integrity or having to figure out what the hell a gtl ref voltage is and how exactly to change it.!
those values are probably safest for most, if you increase gtlref 1 you would most likely need to increase gtlref 0 a smaller amount since ringback is usually never as bad on the low clock since the input voltages are between 0 and (gtlref - crossing threshold), where as the high clock ringback is much greater since the voltages are between (gtlref + crossing threshold) and vtt.
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