How to set up GTL Ref Values for 45nm & 65nm

[vox]

Same way.

Ok any ideia on the value were to start, 0.630 or 0.610? is there a ref range like the 0.8-1.05 for the nb gtl ref?

[truehighroller]

I was wondering the same thing. I think some one here will tell us but, I think it might be a little lower actually.. Correct me of wrong of course.

[jadeiceman]

On my EVGA 780i mobo, I can't set the GTLVREF to negative numbers, there's only positive numbers. Does it matter? I have a Q9450.

[vox]

Yes you dont put the exact value for GTL's, you need to use Multiper (example, like truhighroller his 0.630x is multiper ! )

You need figure out what multiper you need for e.g. 0.8V

I give fast lesson!

Lets think that your looking for 0.8V gtl's now, and 1st thing that you need to know what VTT/FSB voltage your using!

Lets say that your using 1.24V FSB voltage/VTT

2nd you need to do some very easy math

You are looking for 0.8V GTL for both 0/2 and 1/3 setting

First you try 0.630x X 1.24 (your VTT) = 0.781v

Now you got 0.781 result, But that is not the value that your looking for

Lets put few notch more to our multiper (0.630x, it grows by 0.005x every notch)

You set 0.640x This time to both GTL's, and calculate wich value it gives this time!

0.640 X 1.24v = 0.793 ! We are close now

0.645 X 1.24 = 0.7998 !

0.650 X 1.24 = 0.806 !

This is how you use GTL's, it can be hard to find exact value but all formulas that i have read says that 0.8-1.1 are usually ok?

And now you ended to 0.806! You boot to windows and test does it make any difference

Carepolice man whit too much free time!

On my EVGA 780i mobo, I can't set the GTLVREF to negative numbers, there's only positive numbers. Does it matter? I have a Q9450.

jadeiceman, i thing this is what you are looking for...?

[DemonEyez]

I was wondering the same thing. I think some one here will tell us but, I think it might be a little lower actually.. Correct me of wrong of course.

I was wondering, for CPU GTL Ref voltage the ideal range is between 0.80v and 1.005v as was stated earlier in this topic.
But what's the ideal range for the NB GTL Ref voltage? I get the impression that it's lower than CPU GTL Ref voltage because most of the time is has to be set with a (much) lower multplier (e.g. 65/65/63 or 63/63/58) Is this assumption correct?

[QUOTE=mikeyakame;3353927]ideal nb gtlref for standard Intel values is 0.666x vTT, but there is an extra value for the NB called FSB_SWING which is 0.25x vTT nominal, this is set by the manufacturer and it determines the distance for logical 0 / 1 from gtl ref voltage. it's the swing distance for a switched voltage. It may be that this is based off a divider from the GTLREF NB voltage which has already been reduced by a set of 1% resistors, it would make sense to do something along these lines as too high a vTT would cause too large swing between ground and power, perhaps thats the reason why we use smaller NB GTLREF multipliers or values.

[vox]

[QUOTE=DemonEyez;3361691]

ideal nb gtlref for standard Intel values is 0.666x vTT, but there is an extra value for the NB called FSB_SWING which is 0.25x vTT nominal, this is set by the manufacturer and it determines the distance for logical 0 / 1 from gtl ref voltage. it's the swing distance for a switched voltage. It may be that this is based off a divider from the GTLREF NB voltage which has already been reduced by a set of 1% resistors, it would make sense to do something along these lines as too high a vTT would cause too large swing between ground and power, perhaps thats the reason why we use smaller NB GTLREF multipliers or values.

ok so NB gtl ref, as a optimal range of variation from 0.641-0.689? (0.666 -+ 0.025) x vTT= value to put on the NB GTL Ref field??

[truehighroller]

@Vox I seen some one on the P5Q Thread using a .63 ref for the nb and he had 1.28v pumping through the NB. I still don't know what the ideal setting is though.

[MnM]

Guys I've been reading and reading and still can not make full sense of it all.
I will post below the setting I run 100% stable
Can you please analyse/criticise/recommend the settings?
Basically tell me what is wrong with them and what values they should be.
Once I get the hand of this on my mobo then I can go back and re-read this thread in regards to 0.6X multipliers, which voltage shoud by higher than vcore etc.

Rampage Extreme 501 bios
4 x 2 Diablo D9GTR based
QX9770

Extreme Tweaker Menu

CPU FSB - Manual
CPU Level Up - Auto
FSB: 430
-cpu configuration
-cpu clock skew - Auto
-nb clock skew - Auto
FSB Strap to North Bridge - 333
DRAM FREQUENCY - 1721
DRAM Command Rate - Auto
DRAM Timing Control - Manual
*1st information : 8-7-6-15-Auto-Auto-Auto-Auto
*2nd informaion : all AUTO
*3rd information : all AUTO
DRAM Static Read Control - Auto
DRAM Dynamic Write Control - Auto
-DRAM Skew Control
Ai Clock Twister - Auto
Ai Transaction Booster - Auto
*C/P : A1 A2
*LVL : 07 07

EPU II Phase Control - Auto
-----------------------------------------------------------------
*** Please Key in Numbers or select voltage!***
CPU Voltage - 1.462
Load-Line Calibration - Enabled
CPU PLL Voltage - 1.709
FSB Termination Voltage - 1.45
CPU GTLVref (o) - +40
CPU GTLVref (1) - +50
CPU GTLVref (2) - +50
CPU GTLVref (3) - +40
NB GTLVref - +30
North Bridge Voltage - 1.66997 (needs to be this high due to 8GB DDR3)
DRAM Voltage -1.96156
NB DDRVref - Auto
DDR3 ChannelA Vref - Auto
DDR3 ChannelB Vref - Auto
South Bridge 1.5 Voltage - 1.6
South Bridge 1.05 Voltage - 1.08
**********************************************
CPU Spread Spectrum - Disabled
PCIE Spread Spectrum - Disabled

Thanks.

[mikeyakame]

i'm just stress testing a new everyday overclock I set up earlier as we type. It's one of those "hey I got a cool idea I wonder how it will work in practice overclocks", and so far so good, got through 9mins of prime95 first try, made a few little adjustments and trying again, if im lucky it may just need a couple of changes as I bed it in over the next few days if I notice any irregularities in system behaviour or random errors in windows event viewer. first impressions is for 120mhz less cpu and 1 less multiplier, 20mhz less ram, 43mhz more fsb, and change to higher divider is that the performance is already more consistent and at least as good from some quick linpack and everest testing.

1.38v vTT set in bios ( 1.42v in readout ), 0.63x cpu gtl ref, 0.60x nb gtlref, -20mv dram controller ref, -20mv dram ch a ref, -10mv dram ch b ref, 1.3625v vcc, 1.49v vnb, 1.075v vsb, 1.58v vcpu_pll, 1.50v vsb_pll, 2.24v vdimm (2.28v in readout), common performance level of 7, with a single phase pull in cha ph1 ( pl = 6 ) and and all the others cha ph2-5 and chb ph1-5 all using pl = 7, cha clk skew of -250ps, chb clk skew of -150ps, divider 5:6 333mhz bclk, 7x cpu multi, 1139mhz ddr2 5-5-5-15-45-5-2N, 474mhz fsb, 3318mhz cpu, 102mhz pci-e, dram static read enabled, ai clock twister stronger.

with these current settings I'm finding the higher vtt along with lower vcc, vtt being roughly set inbetween vcc and vnb I'm able to get away with quite a low gtl ref multi for both cpu and nb, and from what I can tell the overall system response in terms of how fast the screen is drawn, bootup time from initializing the boot roms till vista desktop, application performance consistency, and a few other visual and response related things i use to make fine adjustments to specific bus values if needed (sometimes with diff frequencies and voltages delays between mch / pci, or cpu / mch and take a little adjustment to correct).

to say there is a starting value other than the specifications of the hardware is extremely difficult unless you are using all the other intel specified nominal voltages. it's always better to add a little more vTT and obtain the same gtl reference target voltage by means of a smaller multiplier or reducing the amount of mV to the current multiplier in place. this leaves a little more headroom to make fine adjustments if the need arises while you are bedding it in for a few days. i dont think i've ever just made major changes without going back over the next week or two and make minute changes every so often...the craziest part is I've become so used to it I just make adjustments based on a hunch and they usually sort the problem out.

[truehighroller]

i'm just stress testing a new everyday overclock I set up earlier as we type. It's one of those "hey I got a cool idea I wonder how it will work in practice overclocks", and so far so good, got through 9mins of prime95 first try, made a few little adjustments and trying again, if im lucky it may just need a couple of changes as I bed it in over the next few days if I notice any irregularities in system behaviour or random errors in windows event viewer. first impressions is for 120mhz less cpu and 1 less multiplier, 20mhz less ram, 43mhz more fsb, and change to higher divider is that the performance is already more consistent and at least as good from some quick linpack and everest testing.

1.38v vTT set in bios ( 1.42v in readout ), 0.63x cpu gtl ref, 0.60x nb gtlref, -20mv dram controller ref, -20mv dram ch a ref, -10mv dram ch b ref, 1.3625v vcc, 1.49v vnb, 1.075v vsb, 1.58v vcpu_pll, 1.50v vsb_pll, 2.24v vdimm (2.28v in readout), common performance level of 7, with a single phase pull in cha ph1 ( pl = 6 ) and and all the others cha ph2-5 and chb ph1-5 all using pl = 7, cha clk skew of -250ps, chb clk skew of -150ps, divider 5:6 333mhz bclk, 7x cpu multi, 1139mhz ddr2 5-5-5-15-45-5-2N, 474mhz fsb, 3318mhz cpu, 102mhz pci-e, dram static read enabled, ai clock twister stronger.

with these current settings I'm finding the higher vtt along with lower vcc, vtt being roughly set inbetween vcc and vnb I'm able to get away with quite a low gtl ref multi for both cpu and nb, and from what I can tell the overall system response in terms of how fast the screen is drawn, bootup time from initializing the boot roms till vista desktop, application performance consistency, and a few other visual and response related things i use to make fine adjustments to specific bus values if needed (sometimes with diff frequencies and voltages delays between mch / pci, or cpu / mch and take a little adjustment to correct).

to say there is a starting value other than the specifications of the hardware is extremely difficult unless you are using all the other intel specified nominal voltages. it's always better to add a little more vTT and obtain the same gtl reference target voltage by means of a smaller multiplier or reducing the amount of mV to the current multiplier in place. this leaves a little more headroom to make fine adjustments if the need arises while you are bedding it in for a few days. i dont think i've ever just made major changes without going back over the next week or two and make minute changes every so often...the craziest part is I've become so used to it I just make adjustments based on a hunch and they usually sort the problem out.

So, what are you saying here with all this info? My small brain can not grasp what you are saying . Please tell me what you are saying here I am sorry.

[mikeyakame]

[QUOTE=vox;3361757]

[I]

ok so NB gtl ref, as a optimal range of variation from 0.641-0.689? (0.666 -+ 0.025) x vTT= value to put on the NB GTL Ref field??

optimal nb gtl reference voltage, as with optimal cpu gtl reference are only relevant to optimal clock drive amplitudes for optimal clock steps. to understand what I mean by this all you need to know is this...

pci clock amplitude is driven with roughly 100mv which is in respect to it working best either side of a 33mhz step, nb clock (fsb) amplitude is driven with roughly 200mv working best either side of a 66mhz step, dram clock amplitude is driven with roughly 400mv working best either side of a 133mhz step, and lastely cpu clock amplitude is driven with roughly 800mv working best either side of a 266mhz step.

what all this means is when changing the frequency for any of the particular bus' is that if you stick to a window of say 25% either side of that bus' tuned frequency steps, ie for a fsb frequency, 15-20mhz either side of lets say 400mhz base clock (stepped at 66mhz to prevent cross talk with other bus') , 380 - 420mhz will give you the best performance and require the least amount of variance from optimal settings, and most of the time provided the vTT is set to a reasonable enough voltage for your vcc and vnb voltages, then you will find that you can work with 0.63-0.65x for cpu gtl ref, and 0.60-0.63x for nb gtl ref.

it's only when you go outside these boundaries you will find the need to use radical gtl reference, fsb termination voltage, and cpu phase locked loop voltage (pll) to stabilize the system properly. certain fsb frequencies are no go zones unless you have clock drive amplitude adjustment, and even with this you have to set the drive amplitude for the nominal frequency steps you require to shield the fsb clock waves from other external bus clock waves, ie 433mhz or 499mhz fsb drop you smack on with the pci bus clock steps (every other 33mhz step, ie 33mhz, 99mhz, 167mhz, 233mhz, 297mhz and so on..)...all this means is without changing the amplitude the fsb clock is driven at and simply changing the frequency within 10-15mhz of these bands will always wreak system havoc at worst or need ridiculous amounts of extra voltage supply to the nb / cpu and way out gtl references to stabilize the system. if you obey the window either side of each 66mhz step, you will find the system performs better, is more responsive and most importantly you don't need to fully understand the concepts behind the design to make even minor adjustments, just a concept of tuned performance zones and basics of why you change the values and when you might need to change them.

[jadeiceman]

jadeiceman, i thing this is what you are looking for...?

I don't think it is... the first post said that if you had a 45nm Proc, you should use the first equation. In the first equation, he subtracted the two values to get a negative number for the GTLVREF, I have a 45nm proc, so I use that equation, right? I get a number, but it's a negative number (-.0384). However, in my bios, there aren't negative numbers. There are only positive numbers, for example, +40mv, +45mv. But don't I need -40mv?

[truehighroller]

[QUOTE=DemonEyez;3361691]

ideal nb gtlref for standard Intel values is 0.666x vTT, but there is an extra value for the NB called FSB_SWING which is 0.25x vTT nominal, this is set by the manufacturer and it determines the distance for logical 0 / 1 from gtl ref voltage. it's the swing distance for a switched voltage. It may be that this is based off a divider from the GTLREF NB voltage which has already been reduced by a set of 1% resistors, it would make sense to do something along these lines as too high a vTT would cause too large swing between ground and power, perhaps thats the reason why we use smaller NB GTLREF multipliers or values.

Ok so, "0.666x vTT" is the standard right? In other words mine would be .666 x VFSB, which is 1.22 which would equal .8152 right? If so then I should make my 1.30 NBv x the ref for it equal, .8152 which would be, .63~ right? So in other words my gtl ref for the nb should be set to whatever multiplier, multiplied by 1.30 which is my NB voltage that gets me closest to the .8152? All the mumbo jumbo is not needed for me just the math in layman's terms will suffice.

[davidk21770]

[QUOTE=mikeyakame;3361904]

...you require to shield the fsb clock waves from other external bus clock waves, ie 433mhz or 499mhz fsb drop you smack on with the pci bus clock steps...

A few questions...

1. The quoted part of your statement seems to belie your signature's 1st CPU (the RF at 434).

2. I've had a heck of a time getting 430 stable -- which is close to 433. I was planning to keep working up in 5 MHz steps. Are you suggesting that I should jump to 440 or even 445 to get away from the 433 clock harmonic?

(PS... found the CPU PLL Voltage on my DFI. I just didn't read the whole SB voltage line... d'oh. Was really surprised that I didn't have it on the tweaker's nightmare 'er... paradise ).

[clappen]

Can someone help me please? Ihave Asus P5Q-E (0803) with E8400 C0 and 1x2gb hyperX pc8500. I've noticed that if i leave all the GTL options in bios on auto, the system is stable with 1.4v on 4.0ghz, FSB 533 (memory 1:1 1066mhz). But only for 2.5 hours, then i got rounding error 0.4 in orthos. And i think all of this is because of the gtl references, and i really want someone to learn me how it works. I dont have english as native language so that makes it even harder with all the counting etc, bu plz if a kind soul want to help me so i get my new system stable.. I have tried for 3 days now constantly, and this is driving me mad!

[truehighroller]

I'm supprised no one has pounced on answering tha nb gtl ref question yet. I might remember something but, not sure and not reading everything again.

[truehighroller]

Can someone help me please? Ihave Asus P5Q-E (0803) with E8400 C0 and 1x2gb hyperX pc8500. I've noticed that if i leave all the GTL options in bios on auto, the system is stable with 1.4v on 4.0ghz, FSB 533 (memory 1:1 1066mhz). But only for 2.5 hours, then i got rounding error 0.4 in orthos. And i think all of this is because of the gtl references, and i really want someone to learn me how it works. I dont have english as native language so that makes it even harder with all the counting etc, bu plz if a kind soul want to help me so i get my new system stable.. I have tried for 3 days now constantly, and this is driving me mad!

I don't know how different your board is but try these settings ,


ASUS P5Q DLX Template :

JumperFree Configuration Settings
AI Overclock tuner: Manual
CPU Ratio Setting: 9

FSB Strap to North Bridge: 266 "set the memory to what ever you know it can handle for yours"

FSB Frequency: 475 "Set to what you have it at now then try this"

PCI-E Frequency: 103

DRAM Frequency: 1185 "Again set to whatever yours can handle"

DRAM CLK Skew on Channel A1: AUTO
DRAM CLK Skew on Channel A2: AUTO
DRAM CLK Skew on Channel B1: AUTO
DRAM CLK Skew on Channel B2: AUTO
DRAM Timing Control: Manual

1st Information :

CAS# Latency: 5
DRAM RAS# to CAS# Delay: 5
DRAM RAS# Precharge: 5
Activate to Precharge: 15
RAS# to RAS# Delay : auto
Row Refresh Cycle Time: auto
Write Recovery Time: auto
Read to Precharge Time: auto

DRAM Static Read Control: disabled
DRAM Read Training: disabled
MEM. OC Charger: Enabled
AI Clock Twister: Moderate

AI Transaction Booster: 8 "If you use 1:1 memory setting then set this to 11 then once stable drop it to 10 if you can"

Pull-In of CHA PH1: Enabled
Pull-In of CHA PH2: Enabled
Pull-In of CHA PH3: Enabled
Pull-In of CHA PH4: Enabled
Pull-In of CHB PH1: Enabled
Pull-In of CHB PH2: Enabled
Pull-In of CHB PH3: Enabled
Pull-In of CHB PH4: Enabled

CPU Voltage: 1.42
CPU GTL Voltage Reference (0/2): .63
CPU GTL Voltage Reference (1/3): .63
CPU PLL Voltage: 1.56
FSB Termination Voltage: 1.22

NB Voltage: 1.30
NB GTL Reference: AUTO
SBridge Voltage: 1.2
PCIE SATA Voltage: 1.6

Load Line Calibration: Disabled "enabled caused issues galore"
CPU Spread Spectrum: Disabled
PCIE Spread Spectrum: Disabled
CPU Clock Skew : AUTO
NB Clock Skew : AUTO

Advance CPU Settings
CPU Ratio Setting: 9
C1E Suppport: Disabled
Max CPUID Value Limit: Disabled
Intel® Virtualization Tech: Disabled
Vanderpool Technology: Disabled
CPU TM Function: Disabled
Execute Disable Bit: Disabled

[mikeyakame]

[QUOTE=davidk21770;3362295]

A few questions...

1. The quoted part of your statement seems to belie your signature's 1st CPU (the RF at 434).

2. I've had a heck of a time getting 430 stable -- which is close to 433. I was planning to keep working up in 5 MHz steps. Are you suggesting that I should jump to 440 or even 445 to get away from the 433 clock harmonic?

(PS... found the CPU PLL Voltage on my DFI. I just didn't read the whole SB voltage line... d'oh. Was really surprised that I didn't have it on the tweaker's nightmare 'er... paradise ).

yeah i ended up using 431mhz fsb to stabilize that overclock and way too much compensation adjustment across the board to get it working comfortably.

ended up using 112mhz pci-e to prevent the nvidia pll clock signal on my gpu leaking into my cpu clock signal! lol it took me a couple of weeks to figure out that was the actual problem and even that was an accident. i was looking over the gpu's memory register dump to try and make sense of memory timing setting DWORD's in the bios for the unknowns and noticed the pll deviation for i think it was the shader clocks.

long story short I gave up and dropped to 431MHz it was manageable to get working as long as I isolated SBPLL from CPUPLL. I ended up using 1.76v CPUPLL and 1.65v SBPLL to work around the cross chatter between the NB and SB. It was a work around really, and performance was never consistent, i'd get variations of 5 - 10 gigaflops at times through 5 or 6 problems in linpack, during the same run.

i finished up last night stability testing my new settings I wanted to try out, and only took 2 or 3 reboots to make small adjustments to vtt and nb/cpu gtlref to pass 1hr of prime95 before i stopped it and crashed out.

the end result is 474mhz fsb on 12:10 divider, common PL of 7 with CHA PH1 pulled in to 6, 3318mhz cpu 7x multi 1.34v vcc, 1.55v vnb, 1.58v cpupll, 1.50v sbpll, 1.075v vsb, 1.36v vtt, cpu gtlref 0.65x, nb gtlref 0.63x, rest arent all that interesting.

performance is quite good with 3.32ghz and cache/memory latencies are better than I expected from only using 1140mhz 5-5-5-15 on ram. memory latency is down around 52.3ns with 9700 / 8600 / 9500 read / write / copy bandwidths.

[DemonEyez]

[I]

Ok so, "0.666x vTT" is the standard right? In other words mine would be .666 x VFSB, which is 1.22 which would equal .8152 right? If so then I should make my 1.30 NBv x the ref for it equal, .8152 which would be, .63~ right? So in other words my gtl ref for the nb should be set to whatever multiplier, multiplied by 1.30 which is my NB voltage that gets me closest to the .8152? All the mumbo jumbo is not needed for me just the math in layman's terms will suffice.

No, you make two errors. You can't calculate NB GTL Ref the same way as CPU GTL Ref.
Just like the CPU GTL Ref voltage, the NB GTL Ref voltage is derived from vTT.
Your calculation is flawed because you calculate as follows:

GTL Increment (in your examle .63) x vNB ( in your example 1.30v) = GTL Ref voltage 0.8152.

So in you calculation NB GTL Ref is derived from vNB and not vTT, that's error one.

Error two is that you asume the GTL Ref voltage needs to be 0.8152v.
For CPU GTL Ref voltage you would be correct, but for NB GTL Ref voltage there one problem:

but there is an extra value for the NB called FSB_SWING which is 0.25x vTT nominal, this is set by the manufacturer and it determines the distance for logical 0 / 1 from gtl ref voltage. it's the swing distance for a switched voltage. It may be that this is based off a divider from the GTLREF NB voltage which has already been reduced by a set of 1% resistors,

So in short, you have to take account for FSB_Swing and with your equation you do not.

Because it's unclear what the ideal range is and how it's calculated, i'm afraid it's trial and error.
A good starting point would be to asume that NB GTL Ref Voltage range has to be set lower than the CPU GTL Ref voltage range.
For 500FSB 1.30vTT and 1.41vNB setting NB GTL to 0.61x works best for me and
for 600FSB 1.36vTT and 1.45vNB setting NB GTL to 0.58x works best

I hope I explained it clearly for you.

If i made an error in my explanation please tell me so. It's just my interpretation of the info provided by Mikeyakame

[vox]

[QUOTE=mikeyakame;3363387]

yeah i ended up using 431mhz fsb to stabilize that overclock and way too much compensation adjustment across the board to get it working comfortably.

ended up using 112mhz pci-e to prevent the nvidia pll clock signal on my gpu leaking into my cpu clock signal! lol it took me a couple of weeks to figure out that was the actual problem and even that was an accident. i was looking over the gpu's memory register dump to try and make sense of memory timing setting DWORD's in the bios for the unknowns and noticed the pll deviation for i think it was the shader clocks.

Hello mike!

So can we say that there is a relation bettewen the PCIE Frequency and the
FSB Strap To North Bridge???

ie: fsb to nb = 431 so pcie freq= 112
or fsb to nb= 466 so pcie freq=101????

if so how do we calculate it for varios values?

tks
vox

[mikeyakame]

i agree with that guy too! nb gtlref calculation is not exactly a science, well even less so than the cpu counterpart. i have a few simple guidelines i follow when setting the nb gtlref value...

1. you will almost never need to use a higher value than cpu gtlref unless you are attempting to use fsb frequencies which don't want to be used! if thats the case change the fsb frequency it's an actual solution to your problem! its so much easier than jacking voltages all over the place to find stability when it's in fact hiding from you because it lies about its good looks and fun times to feel a sense of importance!
2. set a multiplier/voltage that I know will cover the worst case scenario and change it once i've stabilized the other values.
3. set a reasonably high vnb as a base value , i usually go at least 0.05-0.06 higher than I guestimate I'll actually need, sometimes 0.08-0.1v if I am messing with performance level phase pull ins since they more often than less result in data corruption if the clock phases are even mildly deskewed at low performance levels.
4. rounding errors in prime95 usually reflect one of two situations, your vcc is simply too low and thats the first thing i would increment by a step or 2, or the other is that a combination of vtt / nb gtlref , nb gtlref / cpu gtlref, or vtt / cpu gtlref are out by a small amount. then there is rounding errors that are extremely far from the expected value, thats when you know the gtl reference voltages you set are way off or the vtt you set is probably at least -+ 0.04v of where it needs to be.
5. its easier to work with higher vtt voltages and lower gtl ref voltages/multis as they are more likely to register valid clocks in wider working ranges and more importantly makes coarse tuning the supply voltages easier.

prime95 will be the easiest way to find the sweet spot for either reference voltage, you just need to be patient and either note or remember when the last error you got was, and only change one setting at any given time either direction of your previous setting that got you an error. if going 0.01 - 0.03x either side nets you no changes, vcc or vnb need a step or 2 more. don't do too much at once or you'll never know what the problem is, and next time you wont know how to fix it again if it arises. nb gtl ref that is smaller than the minimum you need can be seen visually through what appears to be either hung processes or anomalies in the order than events occur from the moment an image or window is drawn, if it looks wrong then theres a good chance it isnt right!

[clappen]

mike if u could help me plz..

I have changed some values in my bios, and looked into this some. Am i right if i count like this:

GTL (0/1) 0.675 x vTT (1.24) = 0.837 GTL ref. Is that right?

And if it is right, i have two of those GTL:s, i suppose they are for both of the cores. But the first one has standard value of 0.63, and the other has 0.67. How come?

And also, how can i determine what GTL ref to use? I have no idea really.

Sorry for my bad english, hope u understood though..

My setup: Asus P5Q-E, E8400 and Kingston HyperX PC8500. Right now fsb 533 (1:1), stable for 2 hours but no more.

[mikeyakame]

[QUOTE=vox;3363500]

Hello mike!

So can we say that there is a relation bettewen the PCIE Frequency and the
FSB Strap To North Bridge???

ie: fsb to nb = 431 so pcie freq= 112
or fsb to nb= 466 so pcie freq=101????

if so how do we calculate it for varios values?

tks
vox

there is no way to calculate those kind of values. i used 112mhz for pci-e at 431 because it was the only frequency that in hd tune pro didn't appear to have erratic spikes in hard drive read speeds or access, also my gpu didnt magically drop the display out of nowhere while my system was idle.

avoid changing pci-e if you can unless you can say for certain the rest of the system is stable. at least if anomalies appear its a matter of making minor adjustments to the southbridge core voltage or sb pll voltage, if you do change sb pll voltage, change the cpu pll voltage by the same amount more to maintain the gap mainboard engineers design into the system to isolate each pll from the other and vice versa.

changing the pci-e freq more than 5mhz can wreak havoc if devices on the pci-e or southbridge don't tolerate more than a few mhz deviation from the 100mhz base clock. some hard drives will drop off the bus randomly or corrupt data if their controllers design can't work with more than 104-105mhz.

[vox]

[QUOTE=mikeyakame;3363539]

there is no way to calculate those kind of values. i used 112mhz for pci-e at 431 because it was the only frequency that in hd tune pro didn't appear to have erratic spikes in hard drive read speeds or access, also my gpu didnt magically drop the display out of nowhere while my system was idle.

avoid changing pci-e if you can unless you can say for certain the rest of the system is stable. at least if anomalies appear its a matter of making minor adjustments to the southbridge core voltage or sb pll voltage, if you do change sb pll voltage, change the cpu pll voltage by the same amount more to maintain the gap mainboard engineers design into the system to isolate each pll from the other and vice versa.

changing the pci-e freq more than 5mhz can wreak havoc if devices on the pci-e or southbridge don't tolerate more than a few mhz deviation from the 100mhz base clock. some hard drives will drop off the bus randomly or corrupt data if their controllers design can't work with more than 104-105mhz.

for a Q9550 and a P5Q3 Dlx is there a range like 100-105 or 100-113?

i dont have sb pll vol only cpu pll, his there a value that corresponds to it?

my specs:

Overclocker Tuner: Manual
CPU Ratio Setting: 8.5
FSB Frequency: 495
PCIE Frequency: 100 (i think this is the only value to go higher as it is! 102 blocks)
FSB Strap To North Bridge: 333
DRAM Frequency: ddr3-1585mhz the 2ª highest
DRAM CLK Skew on Channel A1: Auto
DRAM CLK Skew on Channel A2: Auto
DRAM CLK Skew on Channel B1: Auto
DRAM CLK Skew on Channel B2: Auto
DRAM Timing Control: Manual

CAS Latency: 7
DRAM RAS to CAS Delay: 7
DRAM RAS Precharge: 7
DRAM RAS Activate to Precharge: 18
RAS TO RAS Delay: Auto
Row Refresh Cycle Time: AUTO
Write Recovery Time: Auto
Read To Precharge Time: Auto
DRAM Static Read Control: Disabled
DRAM Dynamic Write Control: Disabled
DRAM Read Training: Disabled
DRAM Write Training: Disabled
MEM OC Charger: ENABLE
Ai Clock Twister: auto
AI Transaction Booster: AUTO

CPU Voltage: 1.42
CPU GTL Voltage Reference (0/2): Auto
CPU GTL Voltage Reference (1/3): Auto
CPU PLL Voltage: 1.70
FSB Termination Voltage: 1.6
DRAM Voltage: 2..5
NB Voltage: 1.4
NB GTL Voltage: Auto
SB Voltage: auto
PCIE SATA Voltage: auto
Load-Line Calibration: Enabled
CPU Spread Spectrum: Disabled
PCIE Spread Spectrum: Disabled
CPU Clock Skew: AUTO
NB Clock Skew: AUTO

tks
vox

[clappen]

I have changed some values in my bios, and looked into this some. Am i right if i count like this:

GTL (0/1) 0.675 x vTT (1.24) = 0.837 GTL ref. Is that right?

And if it is right, i have two of those GTL:s, i suppose they are for both of the cores. But the first one has standard value of 0.63, and the other has 0.67. How come?

And also, how can i determine what GTL ref to use? I have no idea really.

Sorry for my bad english, hope u understood though..

My setup: Asus P5Q-E, E8400 and Kingston HyperX PC8500. Right now fsb 500 (1:1).

In prime95 i get rounding error after 1.5h, 0.5 expected less than 0.4. So what do u suggest i would change in my bios? The NBv is right, so is the Vcore and my memory. Could it be the GTL:s, or i have too low vtt? i have it at 1.28 now