How to set up GTL Ref Values for 45nm & 65nm

[mikeyakame]

mikeyakame

I'm reading that to help with ringing, Intel connects the clock signal to a pull-up of VCore for one clock cycle on 0->1 transitions -- then it is removed and the signal settles to VTT. (Seems like this will help rise rate also.)
(http://edgeofstability.com/articles/.../gtl/gtl3.html)

If VTT is already ~Vcore, this won't have much effect?
Seems like it'll have reduced noise margin because it'll have more ring?

Correct it does have a weak pull up driver but it does very little at high voltage, and i've found its more effective to rely on vTT acting as a limiter rather than the pull up driver tied to vCC. This seems to minimize transient overshoot from the pull up drivers inability to control the fluctuations at decent voltages above VID(max). Signal noise is expected at higher vCC and can't really be avoided no matter how hard we try. All we can do is adjust the area above the points where the slew rate is determined on the waveform (the points the slew rate is determined should split the ringback threshold range and the valid logical 0/1 range) and try to make sure that by doing what we are doing for that base clock frequency that all the criteria for validity meets what is expected. We can't know for certain but we can blindly figure it out by linpack, prime95, and other apps. All criteria meet when there is no errors or unpredictable behaviour.

I think I understand now what the DFI settings actually refer to. GTLREF Pull Up resistor resistance (ohms). By changing the resistance of the pull up resistor you effectively change GTL Ref voltage provided Icc_gtlref (current) is locked to a constant value. Typical is 124ohm, so to reduce the voltage you would increase the resistance or the value, and to decrease you would reduce the value.

> 0.667 * 1.20 (gtlref multiplier * vtt = gtlref voltage)
ans = 0.8004

> 0.8004 / 124 (gtlref voltage / resistance = gtlref current)
ans = 0.00645484

> ans*112 (gtlref current * 112ohm resistance = reduced gtlref voltage)
ans = 0.722942

this seems to make sense at this time of night! I havent really looked properly at an older DFI bios so If somebody wants to clarify this for me. I just worked it out by quickly looking at the values and finding a value on the datasheet somewhat close to it for agtl+ buffer specs.

This is all I can throw into the pot for the moment, I've been playing The Witcher for too many hours and my head is full of alchemical ingredients and other irrelevant stuff! lol I need some sleep I think! I'll edit this post up in the morning now it's 3.30am and I don't have the mental capacity to think this one all the way through!