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Thread: DFI LANparty DK P45-T2RS/T3RS (Intel P45) - News|Info|Results

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  1. #10
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    Thank you guys for tips. Some good news (below)

    Quote Originally Posted by C-N View Post
    You are quite correct 400/800 & 333/667 are both 1:1 but they use different straps. The 400 strap should be easier to run than the 333 strap but I haven't actually tested it on this board. It wont cost you anything but time to play/try the 333 strap so IMO its worth a go.
    Indeed it was worth of playing. I get bios-posted my rig @ 533MHz Even windows started to loading, ofc it hasn't loaded at all ;]
    Quote Originally Posted by C-N View Post
    I was referring to slackening the timings off from my 2gb setting if you were trying my exact timings as posted. My 4GB kits would not even run tRFC at 28~30 they need to be 46 + to get any joy out of them.
    I used your insane voltages to get this result and most of settings but this time timings was left on auto. My 4GB kit is 1100MHz cl5-5-5-15 by default, so 1066 shouldn't cause instability I guess - am I right? Not sure about tRFC...
    Speaking about voltages, what temp do you have on NB? Mine is ~60 right after turning on, checked in PC Health at bios. Isn't that to much for stable work?

    Quote Originally Posted by GaS View Post
    No one here did not mention anything about the amount of memory shown in Windows XP 32bit...
    Nope you didn't read to fast. There was nothing about this it the thread. Sorry I won't help - 64bit OS here. I recommend to use such xD

    Quote Originally Posted by Alex-Ro View Post
    Yea right,in theory but in practice i am able to hit 650 fsb benchable on air,and in 400/800 i cannot post at all
    Similar here. I can't even post with 400/800. btw. what NB voltage do you use for such high fsb?

    Quote Originally Posted by Blauhung View Post
    these days strap has only minor changes on board since the big one that was traditionally rolled in used to be tRD. Now that it's pulled out, the chipset strap is mostly just for setting memory dividers. I believe it also affects the phase offset applied for clock splitting on the MCH. I think instabilities that come out from these phase offsets are what causes FSB "holes" the majority of the time. Playing with GTL adjustments and timing offsets can sometimes bring you back into a stable regime but this still ends up being wandering in the dark unless you have a good oscilloscope handy.
    Well I heard "something" about this strap-crap thingy... Guess I need to get more knowledge about how it affects stability. I have access to really good oscilloscope or maybe even two But I'm not familiar with use of it. Those are my father's toys ;P Maybe I'll ask him to do some measurement for me or teach me how to do it myself. But I need to know what to measure in the 1st place xD


    Now I'm bit confused. Not sure to replace for the plus version or look more stability with non-plus. For now I've tested 400FSB and it seems to be stable (it wasn't before with 400:800).
    I've run for stability test: 1 core SuperPi 32M and the other core single thread of Prime95 large FFTs (max heat & power...) at the same time. If SuperPi done its calculation successful while Prime still runs without an error I'm starting to consider the setting stable :]


    One more thing, my rig seems to be strongly undervolted.
    Examples:
    NB 1.285V @ BIOS => 1.24V @ SmartGuardian
    VTT 1.26V @ BIOS => 1.23V @ SmartGuardian
    CPU 1.31+V @ BIOS => 1.29V @ SmartGuardian
    RAM 1.908V @ BIOS => 1.88V @ SmartGuardian
    What can cause this, PSU, mobo itself or something else?
    Last edited by tamashumi; 10-09-2008 at 01:34 PM.
    desktop: E8600 (E0), DFI DK T2RS+, G.Skill Pi 2x2GB DDR2-1100MHz, Diamond HD 4870, PCP&C 610Watt Silencer, OCZ SSD core v2 64GB mobile: VAIO SZ650n/c + 2x2GB Corsair DDR2-667MHz

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