Give me an Intel Rig and i sure will. And again the FSB does not limit bandwidth wise, it all depends on the prefetcher and how well its actually working.
"Wrong" Data in the Cache (simplyfied) -> accessing memory -> high latency -> bad coherency -> bad performanceAnandtech:
This is the test that actually screws the whole thing for Intel. It turns out that CBALLS2 calls a function in the Microsoft C Runtime Library (msvcrt.dll) that, when combined with Vista SP1, can magnify the Core architecture's performance penalty when accessing data that is not aligned with cache line boundaries.![]()




. And again the FSB does not limit bandwidth wise, it all depends on the prefetcher and how well its actually working.


Bookmarks