X48 Rampage Formula Preview.

[panheimer]

Can someone teach me about these settings?
I know it's related to Common Performance Level, and have read somewhere that when you can't get to a lower PL, you may try enable these settings to get better performance.
Well, i've setted to 450x8, fsb strap 266 and ram @1125, with a PL7. Wather i put in, settings a PL6 hangs the system on "det dram".
So i've started playing with PL7 and these Pull-IN of CHA...and got something out of it with these settings:
Pull-In of CHA PH1: Enabled
Pull-In of CHA PH2: Disabled
Pull-In of CHA PH3: Enabled
Pull-In of CHA PH4: Enabled
Pull-In of CHB PH1: Enabled
Pull-In of CHB PH2: Disabled
Pull-In of CHB PH3: Disabled
Pull-In of CHB PH4: Enabled
So i was able to enable five of these pull in, with a gain in everest of about 100 MB/s in read and 2.0 ns in latency, while other results remain more or less the same.
If i try to enable CHA PH2, CHB PH2 and CHB PH3 the system hangs on det dram again. Well, i supposed tha if i can enable CHA PH3 i would be able to enable also CHB PH3, but it's not true...why?

[Clump]

Here's my 24/7 overclock. It's 2 hours OCCT stable and 8 hours + prime stable.

Running the 0406 beta BIOS.

Settings:

AI Overclock Tuner.............................. Manual
CPU Ratio Setting............................... 10.0
FSB Strap to North Bridge....................... 333MHz
FSB Frequency................................... 400MHz
PCI-E Frequency................................. 101MHz

DRAM Frequency.................................. DDR2 – 961MHz
DRAM Command Rate............................... 2N
DRAM CMD Skew on Channel A...................... Auto
DRAM CMD Skew on Channel B...................... Auto
DRAM CLK Skew on Channel A...................... Auto
DRAM CLK Skew on Channel B...................... Auto
DRAM Timing Control............................. Auto
DRAM Static Read Control........................ Ensabled
AI Clock Twister................................ Strong
AI Transaction Twister.......................... Manual

Common Performance Level.................... 07
Pull-In of CHA PH1.......................... Disabled
Pull-In of CHA PH2.......................... Disabled
Pull-In of CHA PH3.......................... Disabled
Pull-In of CHA PH4.......................... Disabled
Pull-In of CHB PH1.......................... Disabled
Pull-In of CHB PH2.......................... Disabled
Pull-In of CHB PH3.......................... Disabled
Pull-In of CHB PH4.......................... Disabled

CPU Voltage..................................... 1.48125V
CPU PLL Voltage................................. 1.54V
Northbridge Voltage............................. 1.35V
DRAM Voltage.................................... 2.10V
FSB Termination Voltage......................... 1.32V
South Bridge Voltage............................ Auto
SB 1.50V Voltage................................ Auto
Loadline Calibration............................ Disabled
CPU GTL Voltage REF............................. 0.63x
NB GTL Voltage REF.............................. 0.67x
DRAM Controller Voltage REF..................... Auto
DRAM Channel A Voltage REF...................... DDR_REF + 10mV
DRAM Channel B Voltage REF...................... DDR_REF + 10mV

CPU Spread Spectrum............................. Disabled
PCI-E Spread Spectrum........................... Disabled

My memory would not run at 1066. Prime would error out on blend. I'd like to get it to 1000, but the 266 strap won't boot. There's some more tweaking to do on the memory side.

My north bridge is HOT. I have the included ASUS fan on the regulators and 2 40mm fans directly on the north bridge. After an hour of OCCT it's 66C! It idles in the low 50s. Lower voltages lead to instability, so that's it for now. Once I get the ambition to tear everything apart I'll put a water block, or aftermarket cooler on it. My hottest core was 57C after the 8 hour prime95 run.

[mikeyakame]

Can someone teach me about these settings?
I know it's related to Common Performance Level, and have read somewhere that when you can't get to a lower PL, you may try enable these settings to get better performance.
Well, i've setted to 450x8, fsb strap 266 and ram @1125, with a PL7. Wather i put in, settings a PL6 hangs the system on "det dram".
So i've started playing with PL7 and these Pull-IN of CHA...and got something out of it with these settings:
Pull-In of CHA PH1: Enabled
Pull-In of CHA PH2: Disabled
Pull-In of CHA PH3: Enabled
Pull-In of CHA PH4: Enabled
Pull-In of CHB PH1: Enabled
Pull-In of CHB PH2: Disabled
Pull-In of CHB PH3: Disabled
Pull-In of CHB PH4: Enabled
So i was able to enable five of these pull in, with a gain in everest of about 100 MB/s in read and 2.0 ns in latency, while other results remain more or less the same.
If i try to enable CHA PH2, CHB PH2 and CHB PH3 the system hangs on det dram again. Well, i supposed tha if i can enable CHA PH3 i would be able to enable also CHB PH3, but it's not true...why?

The reason you cant pull in CHB PH3 is because there isn't enough skewing to correct CHB clock phases. You can try adjust CHB CLK skews with a little advance and see if it helps. Be warned if you set tRD phase skewing too tight you will corrupt your CMOS instantaneously, be sure to use OC Profiles to save your settings before you try too tight phase skewing. Try changing your strap also, 266 strap is a bit meh. I use 333 or 400 I find they are better at higher FSBs.

There is also a rule that applies that you must pull in PH1 of either before you are allowed to pull in any other phases or you cause misalignment.

[panheimer]

... Be warned if you set tRD phase skewing too tight you will corrupt your CMOS instantaneously,....

???it's a bit scaring! What do you mean? That i would have to simply clear cmos or that i corrupts bios and have to reflash it?

And what each phase is intended to do? In wich way they affects performance?
I've found that PH1 improves read bandwidth and PH3 improves latency while PH4 seems to do nothing. Is it true or was only my impression?

[panheimer]

The reason you cant pull in CHB PH3 is because there isn't enough skewing to correct CHB clock phases. You can try adjust CHB CLK skews with a little advance and see if it helps. Be warned if you set tRD phase skewing too tight you will corrupt your CMOS instantaneously, be sure to use OC Profiles to save your settings before you try too tight phase skewing. Try changing your strap also, 266 strap is a bit meh. I use 333 or 400 I find they are better at higher FSBs.

There is also a rule that applies that you must pull in PH1 of either before you are allowed to pull in any other phases or you cause misalignment.

As you suggested i've tried correcting CHB skew, but even with 50 advance i immediately got the cmos corrupted...tried higher advance but worthless always corrupt cmos. si i've tried to delay CHB skew, no more cmos corruption but still hang on det dram and no post.
in the end, with my current settings i'm not able to enable CHB PH3, and while priming with CHA PH3 enabled i've got a bsod...so i've disabled also CHA PH3.
BTW now i can confirm that with a 4:5 multiplier on ram, the PH3 affects memory latency: with CHA PH3 enabled i've reached 50.4 ns, while now with it disabled i've returned to 52.2 while cache L1 and L2 remained at 0.8 and 3.2 in with both cases.

[mikeyakame]

As you suggested i've tried correcting CHB skew, but even with 50 advance i immediately got the cmos corrupted...tried higher advance but worthless always corrupt cmos. si i've tried to delay CHB skew, no more cmos corruption but still hang on det dram and no post.
in the end, with my current settings i'm not able to enable CHB PH3, and while priming with CHA PH3 enabled i've got a bsod...so i've disabled also CHA PH3.
BTW now i can confirm that with a 4:5 multiplier on ram, the PH3 affects memory latency: with CHA PH3 enabled i've reached 50.4 ns, while now with it disabled i've returned to 52.2 while cache L1 and L2 remained at 0.8 and 3.2 in with both cases.

nice work! all you can do I suppose is give it more vNB, that's the only way to tighten up PL any farther.

[panheimer]

nice work! all you can do I suppose is give it more vNB, that's the only way to tighten up PL any farther.

no way, every time i got stuck to det dram i've never managed to get around it, tried upping vNB to 1.56 (i'm using 1.41, but think i can still lower it once i find a good setup) and played also with PLL, VTT and both GTLs but never managed to make it post...
maybe you do know a trick to avoid det dram?

[mikeyakame]

no way, every time i got stuck to det dram i've never managed to get around it, tried upping vNB to 1.56 (i'm using 1.41, but think i can still lower it once i find a good setup) and played also with PLL, VTT and both GTLs but never managed to make it post...
maybe you do know a trick to avoid det dram?

a trick! if only. performance level seems dependent on how good quality the ICs on the dimms are. I cant get mine to post with PL6 above 400 fsb, and i've tried for hours. perhaps there is something simple I overlooked dunno. I always use 333/400 strap though. Perhaps that is why. I find they are the most stable but also internal MCH timings are tighter when using either of these 2 straps, so maybe that is why PL6 is hard to achieve. I can run PL7 at 490fsb no problems, but PL6 doesn't ever want to get past det dram.