AMD 45nm Deneb Pictures, CPU-Z and Super Pi Results

[Helmore]

For Deneb to be >= to Yorkfield, it'll need to be 15 - 20% faster than 65nm Phenoms. This seems a bit unrealistic, when was the last die shrink (even with core enhancements + cache increases) that yielded a 15 - 20% increase in performance? Northwood was about 10% faster than Willamette, thats the biggest I've seen from a die shrink. In more recent times, Penryn is some 5 - 6% faster than Conroe. Off the top of my head, I don't remember any AMD die shrinks that have resulted in significantly improved performance, in fact performance went down slightly in the last K8 shrink from 90nm to 65nm.

Now obviously Deneb will increase performance some, the larger L3 alone guarantees that, but all I'm saying is that 15 - 20% is a LOT to ask for. K8 to K10 improved by about that margin per clock, and we're talking an architectural overhaul. You're asking for the same increase from a die shrink + some enhancements, it seems a bit optimistic IMO but time will tell. I personally think Deneb will be 5 - 10% faster per clock, putting it around Kentsfield levels but slightly slower than Yorkfield. Hopefully I am wrong and Deneb lives up to the hype you guys are heaping on it, but I've sort of lost confidence in AMD's ability to deliver, especially on the CPU side of things.

Yeah I also believe that a 5-10% increase in IPC is more realistic for Deneb, although the average will probably be closer to that 5% increase and DDR3 could increase that a little.
About that K8 shrink from 90 to 65 nm., AMD did not want to invest anything into that shrink and they only did the necessary things to get it working on 65 nm. and no optimizations at all. I believe they could have made their 65 nm. part on par of higher performance per clock compared to their 90nm. part but this was probably not worth the hassle. Getting a mature 65 nm. process up and running for Phenom was probably more important, though even there they haven't gone to the same extent as they did with their 90 nm. process and are now primarily focusing on their upcoming 45 nm. process.

@Rammsteiner: Is there any word on the clocks of the L3 cache on Deneb? Is there still a clock deficit between the L3 cache and the cores? I believe they could get a nice boost by clocking them at the same speeds, nothing ground braking probably and a downside might be a decrease (over)clocking potential. But these are all changes to the overall architecture of the chip, the cores them self could use a healthy boost and I don't think that adding some SSE instructions will do so right now.