**Official DFI LanParty UT X48-T2R(and LT) Discussion

[TouGe]

Does anyone have any clues as to how I can run a Performance Level of 6? Is it even possible to run a PL of 6 @ 400FSB using 2GB sticks? Here are my current BIOS settings:

CPU Feature
Thermal Management Control:  Disabled
PPM(EIST) Mode:  Disabled
Limit CPUID MaxVal:  Disabled
CIE Function:  Disabled
Execute Disable Bit: Enabled
Virtualization Technology: Disabled
Core Multi-Processing: Enabled

Exist Setup Shutdown:  Mode 2
Shutdown after AC Loss:  Disabled
CLOCK VC0 divider:  Auto
CPU Clock Ratio Unlock:  Enabled
CPU Clock Ratio: 9.5x
Target CPU Clock: 3800MHz
CPU Clock: 400MHz
Boot Up Clock: Auto
DRAM Speed: 266/667
Target DRAM Speed: 1003MHz
PCIE Clock: 110MHz
PCIE Slot Config: 4x NC

CPU Spread Spectrum: Disabled
PCIE Spread Spectrum: Disabled
SATA Spread Spectrum: Disabled

Voltage Settings
CPU ViD Control: 1.30625V (1.32V)
CPU VID Special Add: Auto
DRAM Voltage Control: 2.00V (1.95V)
SB Core/CPU PLL Voltage: 1.510V
NB Core Voltage: 1.304V (1.32V)
CPU VTT Voltage: 1.100V (1.10V)
Vcore Droop Control: Enabled
Clockgen Voltage Control: 3.45V
GTL+ Buffers Strength: Strong
Host Slew Rate: Weak
GTL REF Voltage Control: Enabled
x CPU GTL1/3 REF Volt: 65
x CPU GTL 0/2 REF Volt: 64
x North Bridge GTL REF Volt: 48

DRAM Timing
Enhance Data transmitting: Fast
Enhance Addressing: Fast
T2 Dispatch: Enabled

Clock Setting Fine Delay
Ch1 Clock Crossing Setting: More Aggressive
DIMM 1 Clock fine delay: Current
DIMM 2 Clock fine delay: Current
Ch 1 Command fine delay: Current
Ch 1 Control fine delay: Current
Ch1 Command fine delay: Current

Ch2 Clock Crossing Setting: More Aggressive
DIMM 3 Clock fine delay: Current
DIMM 4 Clock fine delay: Current
Ch 2 Command fine delay: Current
Ch 2 Control fine delay: Current
Ch2 Command fine delay: Current

Ch1Ch2 CommonClock Setting: More Aggressive

Ch1 RDCAS GNT-Chip Delay: Auto
Ch1 WRCAS GNT-Chip Delay: Auto
Ch1 Command to CS Delay: Auto

Ch2 RDCAS GNT-Chip Delay: Auto
Ch2 WRCAS GNT-Chip Delay: Auto
Ch2 Command to CS Delay: Auto

CAS Latency Time (tCL): 5
RAS# to CAS# Delay (tRCD): 5
RAS# Precharge (tRP): 4
Precharge Delay (tRAS): 12
All Precharge to Act: 5
REF to ACT Delay (tRFC): 44
Performance LVL (Read Delay) (tRD): 7

Read delay phase adjust: Enter

Ch1 Read delay phase (4~0)
Channel 1 Phase 0 Pull-In: Enabled
Channel 1 Phase 1 Pull-In:       “
Channel 1 Phase 2 Pull-In:       “
Channel 1 Phase 3 Pull-In:       “
Channel 1 Phase 4 Pull-In:       “

Ch2 Read delay phase (4~0)
Channel 2 Phase 0 Pull-In:  Enabled
Channel 2 Phase 1 Pull-In:       “
Channel 2 Phase 2 Pull-In:       “
Channel 2 Phase 3 Pull-In:       “
Channel 2 Phase 4 Pull-In:       “

MCH ODT Latency: 1
Write to PRE Delay (tWR): 14
Rank Write to Read (tWTR): 11
ACT to ACT Delay (tRRD): 3
Read to Write Delay (tRDWR): 8
Ranks Write to Write (tWRWR): 5
Ranks Read to Read (tRDRD): 5
Ranks Write to Read (tWRRD): 5
Read CAS# Precharge (tRTP): 5
ALL PRE to Refresh: 5

Changes from previously posted settings:
Ch1 Clock Crossing=Ch2 Clock Crossing=CH1CH2 Common Clock=More Aggressive
All Clock/Command fine delays=Current
T2 Dispatch=Enanbled

Here is my Everest Memory Benchmark:

[IMG][/IMG]

I've tried a PL of 6 all pull-ins disabled w/ 5-5-5-12-54 & T2 Dispatch disabled w/ a NB voltage @ 1.40V but I can't boot into windows. Any suggestions?

Also what's the deal with the random C1 hangs with this board? On every cold boot I get a C1 hang which lasts a few seconds then the computer reboots itself and everything is fine. Then on random reboots I get a C1 hang which clears after I reset the computer. Would bumping the NB voltage fix this problem?
I am now 9 hours small FFTs stable and still 5 hours blend stable. I have also ran HCI MemTest 3.6 for 2 hours now w/o errors.

Any suggestions/help???