Quote Originally Posted by adya View Post
are there any guides around for clock fine delay? like a "clock fine delay for dummies" guide? i really cant get my head around how it works. gtl isnt a problem becuase i just follow clunks chart but clock fine delay is a bit of a mystery for me. i did google it but this thread is the only thing that comes up.
closest would be my info at http://i4memory.com/showthread.php?t=4743

Just think of clock fine delay like GTL tuning only difference, is there is no set table to go by like GTL. each memory module, different mem divider, mem clock speed and timings will alter the clock fine delay values. The info at http://i4memory.com/showthread.php?t=4743 just sheds some light on what to do when you hit a memory clock speed/instability ceiling.

Use http://i4memory.com/showthread.php?t=4743 with memtest86+ v2.01 to figure out initially what clock fine delay values will help lessen or eliminate memtest errors.

Weird part is, now i tried QX9650 first time on DFI LT X38, i find it helps stablise FSB too 9x445FSB 32M pi stable so far at CPU VTT 1.28v - no need for crazy CPU VTT volts >1.5-1.6v