New Memory Tweaker for Intel Chipsets

[Spyrus]

On my laptop with chipset P945PM i cannot set CAS5 to anything else with memtest.
Is that a problem of memset or chipset or it is locked by laptop manufacturer?

[FELIX]

...not possible to change Cas# under Windows.
And Linux version is not expect, sorry.

[Spyrus]

On a laptop with P945 cas5 to 4 did almost nothing in latency and read bandwidth. PL was 5. I also changed pl to 6 and 4 .
On 6 i have 5ns less latency but on 4 it is the same with 5 as tested with everest. Although memset reads 4 there is no change in performance.
Is that a chipset limitation?

[FELIX]

2 years ago I launched memset, and I just find this screen: ...



...sorry guys for had made an so horrible tweaker.

[alpha0ne]

2 years ago I launched memset, and I just find this screen: ...
...sorry guys for had made an so horrible tweaker.

It surprises me you still have such a good sense of humour FELIX

[dinos22]

2 years ago I launched memset, and I just find this screen: ...



...sorry guys for had made an so horrible tweaker.

hahahah good one

i tested the latest version on 790i board

everything working perfect mate (once value can't be changed but no big deal you can select it in bios anyways )

[Kunaak]

there any new Memsets other then 35beta?

with bios 1004 of the maximus extreme, the TRFC range use to top out at 80 within memset, now the TRFC range goes down to 110 within the bios, and cannot be displayed within memset anymore.

bios goes beyond the range of memset in bios 1004 of the maximus extreme.

[FELIX]

I add some highers values in tRFC, tRCD, tRP timings for P35/X38 in this version: memset35beta.exe

[KTE]

Felix, what's the lowest register encoded Performance Level possible on P35?

Can you have PL4? (I don't know which address/bit it is)

Why do both of my RAM modules have different PL on bootup?

In 3.5 BETA (downloaded before the above linked one) when I click to only show one set of values for both modules (tick box between A and B), many times it won't change.

Also, how can we check if a value we change in Memset actually changes or if it actually changes to that value?

Thanks

[Kunaak]

I add some highers values in tRFC, tRCD, tRP timings for P35/X38 in this version: memset35beta.exe

hey, how did you do that?
I was already running 35 beta... is this a new build?

either way, it works.
now I can see the new bios values just fine.
TRFC reports all the way to 127 now.
well beyond the bios range, and definatly something new to try out.
thanks.

[FELIX]

what's the lowest register encoded Performance Level possible on P35?

I think it's possible to run at PL 2 with very lower DDR2.

Can you have PL4? (I don't know which address/bit it is)

Yes it's possible.
Performance Level is at OffSet 248h bit[12-8] for Channel A and 648h bit[12-8] for Channel B.

Why do both of my RAM modules have different PL on bootup?

I don't know; with my IP35-PRO, if I boot with my G.Skill PC-6400 at 266Mhz, I got PL3 on channel A and PL4 on channel B...
It's the same with Read Delay Phase Adjust.

In 3.5 BETA (downloaded before the above linked one) when I click to only show one set of values for both modules (tick box between A and B),
many times it won't change.

Is timings on Channel A & B are the same?

Also, how can we check if a value we change in Memset actually changes or if it actually changes to that value?

I don't understand? if you change a timing with memset and click on Apply, the timing is changed immediately.
You can check it with Everest wich show timing in real time.

hey, how did you do that?
I was already running 35 beta... is this a new build?

Yes, it's a new buid wich I add some tRFC values in this morning.

[BenchZowner]

I think it's possible to run at PL 2 with very lower DDR2.

At 1.7Vmch for P35 I can run PL 2 up to 240MHz FSB on 200 Strap on the P5K3 Deluxe.
With more Chipset voltage and better cooling, and some tweaking I believe it's possible to reach ~320MHz FSB with PL2 on P35.
[ don't take it to the bank though, it's just my impression from a quick quick test some months ago ]

[Spyrus]

According to this table
http://www.anandtech.com/mb/showdoc.aspx?i=3208&p=6

Default tRD at strap should be 166 is 4, at strap 133 = 2 and at strap 100 = 0

And according to the equation here
http://www.anandtech.com/mb/showdoc.aspx?i=3208&p=8

tRC - tCL/N > 0 for 200-266MHz on 1:1 divider you can run CAS 3-5 with tRC = 6
On my laptop i can run tRC = 4 for 166 strap (fsb) and cas 4 and divider N=2:1 so there at 133-200
the equation should be tRC-tCL/N = 4-4/2>1 or 0 again.

So you need more juice but the limit of the chipset stops you

[T_M]

Memset 35beta doesnt work well with Skulltrail (D5400XS).
Many settings appear to be able to change, but when you reopen Memset they are back to default.
Let me know if theres anything i can do/send to help.

[DJSUB]

how can i fix this error on vista?




i got it fixed now

[fgw]

Performance Level is at OffSet 248h bit[12-8] for Channel A and 648h bit[12-8] for Channel B.

expected this addr for channel b and implemented it on my modified memtest boot cd.

I don't know; with my IP35-PRO, if I boot with my G.Skill PC-6400 at 266Mhz, I got PL3 on channel A and PL4 on channel B.

felix and kte, i can confirm this for my ab9quadgt too! verified memset readings with a modified memtest boot cd which reads out all memory timings on my board for both cannels and shows a performance level of 9 for channel a and 10 for channel b at the 400MHz i am currently running the fsb.

originally thought felix you might have mixed up something when reading the pl registers on my chipset, but as my own program confirms memset readings it has to be something within bios i guess ...

[Spyrus]

What modified memtest is that than can read PL?
Is there a link?

[Signal64]

I'm confused on EPP timings being displayed in memset 3.5 beta.

Just took a look at the EPP spec and do not see tRFC (Refresh Cycle Time) and most of the other settings listed in memset EPP display being stored in the EPP.

Can you confirm how this is being calculated?

Is it a "best guess" or a known standard?

[FELIX]

You are right, EPP show only tCL, tRCD, tRP, tRAS, tWR, tRC and command Rate.
Other timings in SPD table come from JEDEC.
I show these timings cause I suppose that they are applicate with EPP too.

[FELIX]

I add intel X48 detection ID in this version: memset35beta.exe

And here is new BAR_Edit v:3.0
I add a full save function in this version: now is possible to save
all registers you want (in PCI and/or memory space) in a .ini file,
and possibility to load the save values by WritSav click or at windows startup.
Probably the finale version, I don't see what I can add now.

Eventually, Report me bugs...

[Signal64]

You are right, EPP show only tCL, tRCD, tRP, tRAS, tWR, tRC and command Rate.
Other timings in SPD table come from JEDEC.
I show these timings cause I suppose that they are applicate with EPP too.

No problem with displaying the other SPD settings when viewing the EPP. It has helped me out of a problem already

I'm still learning how the values for something like tRFC are calculated and trying to understand. The value displayed under EPP is correct for that speed but isn't displayed the same under the normal JEDEC SPD memory speed.

So some calculation appears to be happening?

[fgw]

What modified memtest is that than can read PL?
Is there a link?

i have modified the source code of memtest at my own to quickly read out the mem timings as bios has set it up but before windows loads.

memtest was at hand and the sourcecode is straight forward.

modified just the subroutines for the intel p965 chipset. did nothing else as it involves a lot of reading through datasheets. modifying the code is actually the smaller part of work ...

so, no download for your chipset/board. as said before it will work for p965 chipset/boards only!

[RealTelstar]

i have modified the source code of memtest at my own to quickly read out the mem timings as bios has set it up but before windows loads.

memtest was at hand and the sourcecode is straight forward.

modified just the subroutines for the intel p965 chipset. did nothing else as it involves a lot of reading through datasheets. modifying the code is actually the smaller part of work ...

so, no download for your chipset/board. as said before it will work for p965 chipset/boards only!

I have a p965 (still): can you send it to me?

[Spyrus]

Felix on mobile 945PM chipset it cannot detect more than 2048 of memory
and if it is single or dual channel (shows 2048 with 2x1GB or 2x2GB)

[Signal64]

You are right, EPP show only tCL, tRCD, tRP, tRAS, tWR, tRC and command Rate.
Other timings in SPD table come from JEDEC.
I show these timings cause I suppose that they are applicate with EPP too.

I will ask this a different way.

Displaying the non EPP timings is ok.

How are the missing EPP timings calculated for the EPP display?

I ask because I'm seeing a possible error for the tRFC calculation.