What does PLL voltage do?

[s3k0]

pll is a clock generator but which cpu vcore pushing??

[Obitus]

Just for grins, does anyone know where I can find the PLL voltage on my Gigabyte mobo?

[JumpingJack]

Just for grins, does anyone know where I can find the PLL voltage on my Gigabyte mobo?

If Gigabyte programmed your BIOS to set the PLL voltage, it would show up under some advanced menu option.

Jack

[sofarfrome]

The cyan trace is 180 degrees out of phase with the blue trace.

That would be magenta (cyan is blue).

I spend too much time analyzing toner

[CoW]8(0)]

1.5t + pi just shift it over... by pi (180 degrees) with a multipler now of 1.5, this has nothing to do with mulitplying or phase locking. At the node, the waves will be out of phase, not the same frequency, but out of phase for 1/2 multipliers in 1 period of the input wave form... this is not hard.

I.e. sin(2.5t) != sin(1.5t+pi) != sin(t)

Look you are stuck on a semantic ...

At the node where the wave locks, for 1/2 multipliers, one end the waves are instantaneously in phase and on the other end out of phase. If you prefer, forget the term 'phase' althgether .. and simple say x out put waves in 2 periods of the input wave, or x/2, when X is odd it will be non-integer 1/2 multpliers. Not quite how the circuit works, but you can say it.

I apologize if I'm being too indirect. This should clear things up.



The blue line is sin(t) while the green line is sin(1.5t + pi). sin(1.5t + pi) has a frequency 1.5 times larger than that of sin(t), hence the frequency multiplier of 1.5. At the node (where t = 0 and t = 2*pi), the values of both waves do match and according to you are in 'phase lock'.

Take a wave, then superimpose a wave on top of that such that the they both begin and end on zero, that is all you need.

But at t = 0, the waves are going in opposite directions and are exactly pi out of phase (hence the + pi). I guess the main issue is the way you're describing what it is to be 'in-phase' and and 'phase-lock'. The semantics you're using are inconsistent. I think describing the the PLL in terms of frequency rather than periods would simplify it drastically. You're describing it as if you're adding 1/2 a period (ie: pi) to the input to get the output.

And all that's really saying is you're increasing the frequency of the output 1.5 times the input. And this is all that really needs to be said, all the results you describe about 'going in opposite directions' and other characteristics will be a result of that statement. The 1/2 value is of frequency, not of periods or phasing.

[JumpingJack]

But at t = 0, the waves are going in opposite directions and are exactly pi out of phase (hence the + pi). I guess the main issue is the way you're describing what it is to be 'in-phase' and and 'phase-lock'. The semantics you're using are inconsistent. I think describing the the PLL in terms of frequency rather than periods would simplify it drastically. You're describing it as if you're adding 1/2 a period (ie: pi) to the input to get the output.

You are correct, we are arguing semantics, and I understand your plot and why you plot it, bit this is not quite what I am try trying to describe.

A phase lock loop is a closed loop clock generator which uses three things primarily. An input waveform, a frequency divider, and a phase comparator. The phase lock only needs to lock on the same point (typically a node) of the wave form. A traveling wave will cross the same point twice, therefore it is realtively easy straight forward to create a phase lock on 1/2 multiples of the reference wave. This is basically how the PLL sets the frequency.

Now, in terms of the semantics, this is off topic slightly but helps clarify the terms, take two two waves traveling either temporally or spatially, both with the same frequency and they can be phase shifted so that at any point in time or any point in position, they will be pefectly out of phase by some angle... this is what you are describing to a degree. The other situation is when you have two waves but with different frequency, there will be a point when comparing these two that they will be temporarily in phase and temporarily perfectly out of phase, the combination of which is called a beat.

When I describe a whole or half multiplier, it is an illustration how 1/2 multipliers naturally fall out of a wave form within one period when the beginning and end node are in oppositive phases with one enother.

You are not incorrect in apply a phase shift, but in describing how to establish the beat (and the 1/2 multipliers) my terms are still correct just different context -- on that note, comparing sin(t) with the multiplied sin(1.5) or sin(1.5t+pi) is utterly no difference all you did was move, in this context the loop of the PLL is adjust the phase shift as well as adjust frequency to ensure the lock at a predetermined beat.

Jack

[jonny_ftm]

On my Q6600, overclocked to 8x475 for 3.8GHz, my vPLL is fixed to 1.5v. I tried to increase it and it didn't make it possible to lower my vcore neither to lower FSB wall, so really useless except to kill the CPU, much quicker than vcore, at least for me, and suerely for most of you if we do believe the forums and Anandtech tests

[TheScavenger]

This thread is awesome. Thanks to everyone who contributed

[PanzerIV]

Indeed very interesting thread. On my DFI P35 DK-T2RS the PLL voltage is by default at 1.55v and since Intel says the maximum is 1.575v I may try that instead or else won't go above 1.6 for sure now that I know its much more risky than raising other voltage.

Now what would be interesting would be to know what does (Clockgen Voltage Control), mine being set by default to 3.45v

[003]

The cyan trace is 180 degrees out of phase with the blue trace.

If you were to write the functionality of the blue and green it would look like this:

Blue = sin(x) with x in degrees
Cyan = sin(x+180) with x in degrees

180 is refered to as the phase shift, greek character phi is often used.

A PLL must lock onto a node, the simplest explanation is that for this to occur at the node when the wave forms cross at 0, in the same going direction (this would be in phase), this would result in whole multiples of the output wave form. If the PLL locks at the node where the node is going in opposite directions (negative going), it is out of phase....

This is a simple explanation for it... another way to think about it is that the output wave form is in phase with the input wave form ever 2 periods.

Here is a better example of a 2x PLL locked in phase with an integer multiplier.



Jack

Jack, please correct me if I'm wrong, but I'm pretty sure for the sine graph you posted:

Blue = sin(x) with x in degrees
Cyan = -sin(x) with x in degrees

Now if I remember correctly from trig, wouldn't 180 degrees out of phase actually be f(x)=sin(x)+180 or f(x)=sin(x+180).... I don't remember which it is. But I'm pretty sure I'm right on the first part of -sin(x) and sin(x)...

[mikeyakame]

pll voltage is basically just used to limit the distance from nominal alignment for all input phases for a devices output clock signal against a reference frequency from an Analog generator usually that the input base clock signal was oscillated from. higher pll voltages dont work as you would expect, a given pll voltage needs to be with respect to the drive voltage the wave was oscillated with.

now as the amount of active phases increases, jitter gradually becomes an obstacle you cant get around. there's only so much a locking loop can provide, and that's really to limit the skew within the system to a manageable level which doesn't require complicated and expensive components to track with resolutions of less than 125ps, and provide automatic phase skew adjustment. The internal PLL this voltage is applied to, does just this but on a very low level. Instead by locking the extent phases can deskew and keeping them where a constant skew offset will do the job.

[PanzerIV]

It's completely ridiculous on my DFI board for the "PLL Voltage" ...
It's by default at 1.55v and according to Intel I could go up to 1.575v so I was going to set it to this in the bios but they only give me extremly high values. The smallest step after 1.55v would be 1.75v!!! . I seriously wonder wtf DFI thought when they made the bios.

[mikeyakame]

i'm pretty sure the line of thought was something like 1.75v would be the next voltage which won't compromise the stability of the system. you need to be careful when adjusting the CPU PLL voltage, as if there is also an adjustment called SB 1.5V or SB SATA 1.5V, this is the Southbridge PLL voltage and my experience with this is, keep its actual voltage and the CPU PLL actual voltage, at least 0.1v apart. Why you ask? BEcause if you don't the system will behave erratically at best, and at worst you will end up with a system that responds like it's hungover and get random usb device dropouts, gpu instability, and all other things of annoying problems that won't make the system unpostable but it will irritate you to no end.

I try and keep the SB 1.5V PLL lower than 1.70v because on both X48 and P45s i've manually set this on this was about the highest I could go before it began to introduce instability and erratic behaviour. CPU PLL on the other hand I prefer to keep that higher as it can tolerate 1.8-1.9v with a big smile and open arms. 1.60v SB 1.5V, and either 1.52v CPU PPL or 1.70+V CPU PLL.

Try the 1.75V setting it won't damage the CPU if thats what you are worried about. I've run 1.9V on my Asus Rampage Formula for a good week or more, but in the end i Reduced it down to 1.78v or so because there was no benefit from such a high value as even it couldn't fix the inherent vrm phase limitations of the FSB with a quad core. At best it gave me a little more stability, but not enough to prevent full system locks completely. It probably gave me an extra 5-10mins before a hard freeze would set in while running Prime95 or Linpack. This was with 495MHz FSB.

Edit:
I used all my strength and with one hard pull that finger of mine came out, and low and behold I bothered opening up the ICH9R datasheet thats been sitting on my system for months.

So unless the SB 1.5V has more than one adjustment setting, it's more than likely that this voltage setting is a common input voltage to supply all the individual PLL circuits for each source that requires a clock reference.
Without further adue, heres the list of all the PLLs we break or fix by adjusting the SB 1.5V setting on any board sporting a ICH9/10 sb, and courtesy of Intel a generic explanation of each for reference.

VccDMIPLL - 1.5 V supply for core well logic. This signal is used for the DMI PLL. This power may be shut off in S3, S4, S5 or G3 states.
VccSATAPLL - 1.5 V supply for core well logic. This signal is used for the SATA PLL. This power may be shut off in S3, S4, S5 or G3 states. Must be powered even if SATA is not used.
VccGLANPLL - 1.5 V supply for core well logic. This signal is used for the integrated Gigabit LAN PLL. This power is shut off in S3, S4, S5 and G3 states.
VccUSBPLL - 1.5 V supply for core well logic. This signal is used for the USB PLL. This power may be shut off in S3, S4, S5 or G3 states. Must be powered even if USB not used.

After brief realization, a single input voltage to supply all the PLLs on the SB explains the broad range of irritations and problems i can replicate with precision just by accidentally or purposely setting the CPU PLL and SB PLL voltages no less than 0.06-0.07v of each other. The closer you go the worse the onset of the problems, the most annoying but harmless problem is when my USB keyboard becomes the victim of this scenario, and I really need to change settings in the bios but low and behold keys either don't do anything or fall into a repetition loop until you manage to navigate your way through the bios by luck or that the next post you go into the bios you just might be lucky enough that the PLL crosstalking affects something other than your key to fixing the problem

The key to a stable system is destabilizing it and then working out what you actually destabilized, why it impacted half of your system and not the other, then making adjustments if possible to isolate that voltage from any nearby input voltages. Sometimes a distance of 0.01-0.02v is adequate, but with PLL supply inputs a safe buffer would be at least 0.08-0.1v from another other PLL supply voltages used for internal phase deskewing. The only reason I can think of that would satisfy the solution is that the voltage regulation circuitry supplies both traces from a common down-transformed supply. This would account for why the jitter becomes so heavy as those pll supply voltages get nearer to either ones set voltage, and why that jitter exhibits cross talk as the gap drops below 0.05v.

The jitter at the output buffer is most likely the result of the voltage ringing back along the traces length to its source, and the other pll voltage being such a close voltage the ringing / jitter decides "hey, look over there thats our ticket to freedom! that nasty receiver waiting for us will never expect us to switch traces" and before you know it the receiver on the output side is unable to do its job (which happens to be ringback draining) and that small gap in voltage for either supply effectively adds a point for the ringback to easily cross the traces and pollute the other PLL supply since the ringing is always a result of the input side grounding the signal and is usually harmless when it rings towards the output supply, and there will be receivers to handle the filtering of the voltage ring back in most cases. There is no need for these on the input side, and that's why the ringing towards the input turns harmless jitter into super bad ass evil jitter, and no super bad ass evil jitter battling super hero to save the input supply buffer from its path of chaos!

Since not overclocking is hardly a viable option for enthusiast motherboard market that loves overclocking, we are paying the price of overclocking freedom in the premium jump in price for the expensive 6+ layer pcbs our high end boards are generously endowed with. And they say overclocking is all about getting more value from cheaper value parts, while being true with respect to components which we purchase seperately such as the cpu or gpu, it's now becoming offset by the continously rising premiums we are forced to pay for a board. What we save on cheaper hardware components, we are shifting to the motherboard companies so we can justify the satisfaction of a $200 part performing like a $500 one, even though we paid an extra $200 for a board specially designed to eliminate the problems we created when we went outside the design specs of the architecture.

I personally don't mind copping that steep premium if it means the board I'm paying 2-3 times more for has more than adequate overkill designed into it, as long as the engineers designing it are competent enough that the boards design both behaves like the spec requires, and beyond those limits at least tries to work like originally intended to. I'm seeing lots of boards that clock high but don't behave the way they should, this makes for unpleasant overclocking and unexpected behaviour we shouldn't be coming across because it occured simply as a result of taking shortcuts or adding features that double up as trip wires to undocumented flaws. Which were probably not documented because the engineers who designed it originally took a different approach to avoid such a scenario. I don't want to call names so I won't but there are far and few between boards designed to work flawlessly with the architecture its based on, and the rest of the boards which spit the dummy when two settings conflict with each other, and give no end of problems or solutions.

[breetai72]

Several people are getting their terminology confused.

Typically an adjustment for PLL voltage refers to the CPU PLL voltage supply. PLLs are used internally to distribute clocks all over the die. They have their own voltage rail so that it's as clean as possible. Noise on the CPU PLL supply rail will cause jitter and instability. Increasing PLL voltage can also have the effect of increasing the magnitude of noise on the rail, so it may or may not be useful. It depends on how well the voltage regulator was designed.

Many people refer to the system clock generator as "The PLL". This is imprecise. The clockgen is the part on the board that you adjust BCLK, FSB CLK, PCIe CLK, etc. Some motherboard manufacturers provide options to alter the clockgen voltage supply.

[mikeyakame]

That's pretty much spot on. I think I came across saying that! Sometimes it gets lost in translation.

Internal PLL voltage supply for CPU , PCH or MCH would in most cases use a common output from the main voltage regulator if they all require the same supply voltage for their internal pll circuit, and it would make sense that the voltage regulator if the variance in two output voltages is small enough that the fixed resistors for that circuit can finely adjust the voltage received at the pin, then it may not need to down reg it internally or otherwise there is noise on the reg side which is leaking between output pins for similar voltages. If its not at the vreg, then there is also the possibility the noise leaks its way across to the Southbridge as at least 3 or 4 pins are directly connected to the CPU landing pins associated with voltage supply, digital thermal sensor (for peci), and possibly more I can't recall from the top of my head.

Core2 Duo m-arch all the main chips uses a common internal pll supply voltage for I believe all their individual internal pll inputs as I havent come across any I can recall that work on a different supply requirement, which is 1.5V.

I wish I had the necessary logic analyzer setup to say for certain where the problem lies. It would be much less work than speculating a problem that exists but is unknown specifically how it came to be.

[PanzerIV]

i'm pretty sure the line of thought was something like 1.75v would be the next voltage which won't compromise the stability of the system. you need to be careful when adjusting the CPU PLL voltage, as if there is also an adjustment called SB 1.5V, this is the Southbridge PLL voltage and my experience with this is, keep its actual voltage and the CPU PLL actual voltage, at least 0.1v apart.

I try and keep the SB 1.5V PLL lower than 1.70v because on both X48 and P45s i've manually set this on this was about the highest I could go before it began to introduce instability and erratic behaviour.

CPU PLL on the other hand I prefer to keep that higher as it can tolerate 1.8-1.9v with a big smile and open arms. 1.60v SB 1.5V, and either 1.52v CPU PPL or 1.70+V CPU PLL.

Try the 1.75V setting it won't damage the CPU if thats what you are worried about. I've run 1.9V on my Asus Rampage Formula for a good week or more, but in the end i Reduced it down to 1.78v or so because there was no benefit from such a high value as even it couldn't fix the inherent vrm phase limitations of the FSB with a quad core.

Nice! Thanks for that information. I'm not too much into very complex and technical electricity explanations but what's in the quote is easy to understand and is exactly what I wanted to know in order to help my overclock. I just wonder however why on some other forums there was many people saying that we absolutely needed to keep the CPU PLL under 1.9v not to severely damage it, and idealy never above 1.60v not to quickly degrade the cpu. That's why I was scared to try 1.75v but in a other hand, that would had suprised me that DFI offer 1.75 right after the default of 1.55v so it must not be thaaaat dangerous as others were pretending. I just hope you're right lol.

Then I'll raise my SouthBridge 1.5v to 1.6v like you suggested me. That could be the key for going at 4.40Ghz and above without having prime to get an error everytime after 17min of blend test... because raising all the other common voltage (VTT, Vcore, Northbrige, ClockGen Voltage Control) didn't help at 4.4xGhz.

I tryed however to raise ClockGen from 3.45 to 3.60v and VTT from 1.20 (default 1.10) to 1.30v and at 4.32Ghz I think its what made my blend not get any errors like it did previously after 10 houres. Small FFT in Prime would also get error after 10min and now I could easily do many houres without problem so it must have still helped. I don't think I would need to raise the VTT any higher since 0.2v is still already a high voltage bump.

[PanzerIV]

Heh.. it would had been to great to be exactly just like how you said. I went back into my bios and for the Southbridge there was only two voltage settings. One for PLL which is the one I had by default 1.55v and raised to 1.75v as you suggested me, and the other one being "Southbridge 1.05v", not "1.50v". The available values for this setting were: 1.07 being the default, then 1.15, 1.217 and 1.30v

So there's just no way to set it at a number that will end up doing a diffrence of 0.1v with the PLL. Usualy just going 1 step up from default shouldn't be harmful so I'm trying SB 1.15v and PLL 1.75v, but tell me if these value are wrong or too high please, as last thing I want is to wake up one day with a degraded cpu.

Edit: So I've tryed these value and even disabled completly EIST and also upped the VTT from 1.30 to about 1.33 (real = 1.31) and at 4.43Ghz it again caused an error at 17min in Prime. Goddamnit no matter what I seem to raise it doesn't want to get stable over 4.32Ghz ... so shall I just try to find the minimum voltage required to stay stable at 4.32Ghz after all? Because I just can't seem to get stable any higher and I sure don't want to add A LOT more voltage just for a small 100Mhz increase..