What does PLL voltage do?

[CoW]8(0)]

1.5t + pi just shift it over... by pi (180 degrees) with a multipler now of 1.5, this has nothing to do with mulitplying or phase locking. At the node, the waves will be out of phase, not the same frequency, but out of phase for 1/2 multipliers in 1 period of the input wave form... this is not hard.

I.e. sin(2.5t) != sin(1.5t+pi) != sin(t)

Look you are stuck on a semantic ...

At the node where the wave locks, for 1/2 multipliers, one end the waves are instantaneously in phase and on the other end out of phase. If you prefer, forget the term 'phase' althgether .. and simple say x out put waves in 2 periods of the input wave, or x/2, when X is odd it will be non-integer 1/2 multpliers. Not quite how the circuit works, but you can say it.

I apologize if I'm being too indirect. This should clear things up.



The blue line is sin(t) while the green line is sin(1.5t + pi). sin(1.5t + pi) has a frequency 1.5 times larger than that of sin(t), hence the frequency multiplier of 1.5. At the node (where t = 0 and t = 2*pi), the values of both waves do match and according to you are in 'phase lock'.

Take a wave, then superimpose a wave on top of that such that the they both begin and end on zero, that is all you need.

But at t = 0, the waves are going in opposite directions and are exactly pi out of phase (hence the + pi). I guess the main issue is the way you're describing what it is to be 'in-phase' and and 'phase-lock'. The semantics you're using are inconsistent. I think describing the the PLL in terms of frequency rather than periods would simplify it drastically. You're describing it as if you're adding 1/2 a period (ie: pi) to the input to get the output.

And all that's really saying is you're increasing the frequency of the output 1.5 times the input. And this is all that really needs to be said, all the results you describe about 'going in opposite directions' and other characteristics will be a result of that statement. The 1/2 value is of frequency, not of periods or phasing.

[JumpingJack]

But at t = 0, the waves are going in opposite directions and are exactly pi out of phase (hence the + pi). I guess the main issue is the way you're describing what it is to be 'in-phase' and and 'phase-lock'. The semantics you're using are inconsistent. I think describing the the PLL in terms of frequency rather than periods would simplify it drastically. You're describing it as if you're adding 1/2 a period (ie: pi) to the input to get the output.

You are correct, we are arguing semantics, and I understand your plot and why you plot it, bit this is not quite what I am try trying to describe.

A phase lock loop is a closed loop clock generator which uses three things primarily. An input waveform, a frequency divider, and a phase comparator. The phase lock only needs to lock on the same point (typically a node) of the wave form. A traveling wave will cross the same point twice, therefore it is realtively easy straight forward to create a phase lock on 1/2 multiples of the reference wave. This is basically how the PLL sets the frequency.

Now, in terms of the semantics, this is off topic slightly but helps clarify the terms, take two two waves traveling either temporally or spatially, both with the same frequency and they can be phase shifted so that at any point in time or any point in position, they will be pefectly out of phase by some angle... this is what you are describing to a degree. The other situation is when you have two waves but with different frequency, there will be a point when comparing these two that they will be temporarily in phase and temporarily perfectly out of phase, the combination of which is called a beat.

When I describe a whole or half multiplier, it is an illustration how 1/2 multipliers naturally fall out of a wave form within one period when the beginning and end node are in oppositive phases with one enother.

You are not incorrect in apply a phase shift, but in describing how to establish the beat (and the 1/2 multipliers) my terms are still correct just different context -- on that note, comparing sin(t) with the multiplied sin(1.5) or sin(1.5t+pi) is utterly no difference all you did was move, in this context the loop of the PLL is adjust the phase shift as well as adjust frequency to ensure the lock at a predetermined beat.

Jack

[jonny_ftm]

On my Q6600, overclocked to 8x475 for 3.8GHz, my vPLL is fixed to 1.5v. I tried to increase it and it didn't make it possible to lower my vcore neither to lower FSB wall, so really useless except to kill the CPU, much quicker than vcore, at least for me, and suerely for most of you if we do believe the forums and Anandtech tests