Official GIGABYTE X38-DQ6/X38T-DQ6 Info/BIOS Thread

[Nuckin_Futs]

Is not the mobo that offers that option, is the chipset. X38 is supporting ECC, and non ECC memo, X48 suports only non ECC.

This is partly true. Keep in mind though, it is upto the builder to utilize it and some do not. Just as X48 can by design utilize ECC but is currently locked by Intel but potentially (not for sure) can be cracked by a builder (like ASUS) to unlock that, just like they did for PAT and PRB for Springdale !865PE and PRB for new !925XE Elderwood. Here again, Intel made efforts to lock chipset for CPU to PCI/PCIE lock limiting the FSB overclock. But ASUS cracked it, remember!

I tried ECC before and I wasn't happy with it. It is not necessary for me. RAM is pretty stable as it is and few random errors would not make a big difference in my life or in my work... As for CPU, RAM and all the other hardware where data does not reside, I am not worried. If it broke, replace it.

But I would like to know the consequences of running the system with a higher FSB... I don't mind if the hard drive gets corrupted and does not boot, does not spin, etc... I can fix/replace it. But I would mind if every so few bytes of files were corrupted randomly since I would not be finding about out that right away. And when I find out about that, there would be no way of quantifying how much data was corrupted.

How much standard voltage is on SB? What is SB 1.5?

All the other test can pass with colors, but YES, data corruption can still happen if too many hard lock ups and crashes. These synthetic benchmarks do not test HDD R/W so make sure they too have enough juice to stay smooth. I use at least 1.58v on SB 1.5 and 1.104v on SB 2 to 500FSB on my ASUS. They just need to be kept cool like anything else cause this carries the ICH9R and thats where our DATA crosses if on the Intel AHCI/RAID. I this mobo offers some sort of FSB static read control, enable it to smooth out the CPU to NB strapping curve of mobo as it climbs the higher FSB beyond 450. This will alos help in getting few more MHz FSB out of CPU as well.

The simplest rule is to keep CPU/RAM ratio simple. 1:1 or 1:2. Anything inbetween is not as stable when OC'd. P35, X38/X48 are finicky with out of sync CPU/RAM dividers since the chipset was origionally based on test for DDR3 with different timing control.

Thanks ChrissTi.

So EIST works only when no vcore is set -- simply meaning that when there is no overclocking in most cases.

Why hasn't this been mentioned at anywhere? Why do people advise for turning EIST off during overclocking and turning it back on once a stable oc is achieved if EIST is not even working with oc in the first place?

I never suggest using EIST under an OC system. It is already slower then TM2+C1E so it becomes less responsive as you up the system FSB since it uses the system FSB to function and thus is an added bottleneck in bus traffic. TM+C1E will at least allow TM1+C1E mode so you do get the multi step down but not the cvore. Mine always drop just enough to matter if on all day and also takes up some of the stress on NB and MCH, so overall system can drop some in temp.