Yep, just checked out the guide, quote BKDG:
The processor supports dynamic P-state changes in up to 5 independently-controllable frequency planes: each
CPU core (up to 4) and the NB; and up to 2 independently-controllable voltage planes: VDD, and VDDNB.
MSRC001_0062 holds the P-State transition for each core so you can first define a separate P-State under MSRC001_00[68:64] and then using MSRC001_0062 set a separate P-State from 0-4 for each core individually. So P0 is maximum power state, P1 for core 0, P2 for core 1, P3 for core 2 and P4 for core 3. Quite nifty don't you think?

RWE doesn't work for me, it just gets stuck and deletes the file data.