**Official DFI LanParty UT 790FX-M2R Review/Overclock/Guide Thread**

[KTE]

Yeah that CnQ P-State 1 works realtime. I've messed about with it earlier - old value is RDMSR, new value is WRMSR (stable):



4x is lowest multi limit, freeze below that.
I'll edit post with a full reply in a while, bit busy yet.

EDIT (updated above pic):
That above is lowest voltage for NB/CPU stable too, any lower it freezes.

I'm running near enough exact settings as you Achim, especially CPU settings. My system idles 108W AC @ this:



And with CnQ enabled now in the first pic above, it idles 94W AC (2x HDs, 2x 5V fans). Very good options to access and edit these registers IMHO, don't you think?

Here are my settings I run with those two:

Current: MSR 0xC0010070
0x00000000 0x4800340A (1.100V NB/1.225V CPU)

P0: MSR 0xC0010064
0x800001BC 0x4800340A (1.100V NB/1.225V CPU)

P1: MSR 0xC0010065
0x80000187 0x48007040 (800/1800 0.850V/1.100V)

V above = VID.

As you can see, VIDs is how the processor controls all volts internally even for CPU and NB in all P-States including boot states. So that 1.250VID NB is 1.232V/1.240V. But NB VID never changed in P-State 1 unless you do this manually. I know NB FID cannot be changed after boot and that's why it won't change where HTC is active where GCLK downclocks nor when you have CnQ enabled but ... messing with the NB VID register it works fully, like so:

NB VID Control
30h 0011000b 1.250V
....
38h 1.200V
39h  1.200V
40h 1.150V
41h 1.150V
42h 1.138V
43h 1.138V
44h 1.125V
45h 1.125V
46h 1.112V
47h 1.112V
48h 1.100V
49h 1.100V
50h 1.050V

Those are only ones I can access yet because I don't have my saved ss/txt files here.

I can change CPU DID to 1 and 2 real-time but anything higher is no go.
I've not tried NB DID yet.

Yep, power is controlled by the CPU VID, NB VID, IddValue and IddDiv which also sets the TDP and that changes the Tcontrol and Tcontrol max limits apparently.
BTW I know Tcontrol is not the actual temp value in degrees but just an arbitrary value to represent it. That's why it's allowed to read subzero at high ambients.
What happened was, my first 9500 which is the main one I experimented highly with temps, it read the temp in BIOS the same as the physical Tcase temp most likely because it was missing the offset, but the ones after that were all different. This 9600BE reads the register properly (sub-ambients).

Same with F3xA4, I asked about it because on the NB register access it read 0b for me so I thought there's another way. It reads correctly now but many times it blanks out or reads F's.

Thanks for adding the bits, makes me not have to read the guide. Although you did make me read up the guide once again you know...

[justapost]

EDIT (updated above pic):
That above is lowest voltage for NB/CPU stable too, any lower it freezes.

I'm running near enough exact settings as you Achim, especially CPU settings. My system idles 108W AC @ this:
And with CnQ enabled now in the first pic above, it idles 94W AC (2x HDs, 2x 5V fans). Very good options to access and edit these registers IMHO, don't you think?

Yeah those p-states are great for tweaking, running with one HD and 3xFans atm.

CPU 2.6 (217x12) at 1.3V CPU VID
NB 2.17 (217x10) at 1.3V NB VID
MEM 578MHZ at 2.25V

idle: 157W AC
load: 270W AC

CPU .8 (217x4) at 1V CPU VID
NB 2.17 (217x10) at 1.3V NB VID
MEM 578MHZ at 2.25V

idle: 139W AC
load: 180W AC

Lowest possible consumption is cpu 200x4 at 0.9V nb 200x9 at 0.95V. In idle ~105W AC. So the board still needs more tweaking to beome more efficient.

A note aboute the NB multi. If CnQ is set to Auto in the Bios, the NB multi is always 9x. So it's required to up the ref HT to tune the nb.
However with above scripts it's possible to set the p-states and switch between em manual. Those work with CnQ disabled in bios.
A third p-state would be great, i'd like to have a low normal and high p-state.

Here are my settings I run with those two:

Current: MSR 0xC0010070
0x00000000 0x4800340A (1.100V NB/1.225V CPU)

P0: MSR 0xC0010064
0x800001BC 0x4800340A (1.100V NB/1.225V CPU)

P1: MSR 0xC0010065
0x80000187 0x48007040 (800/1800 0.850V/1.100V)

V above = VID.

As you can see, VIDs is how the processor controls all volts internally even for CPU and NB in all P-States including boot states. So that 1.250VID NB is 1.232V/1.240V. But NB VID never changed in P-State 1 unless you do this manually. I know NB FID cannot be changed after boot and that's why it won't change where HTC is active where GCLK downclocks nor when you have CnQ enabled but ... messing with the NB VID register it works fully, like so:

Is 2.6GHz stable at 1.225V VID?

I can change CPU DID to 1 and 2 real-time but anything higher is no go.
I've not tried NB DID yet.

The predefined p-states differ in the CPU DID and have the same CPU FID, can be it's faster to switch between the modes if only the DID changes.
NB DID must be equal on all cores's and p-states, no way to change the nb speed on the fly.

Yep, power is controlled by the CPU VID, NB VID, IddValue and IddDiv which also sets the TDP and that changes the Tcontrol and Tcontrol max limits apparently.

Have you played with IddValue/IddDiv? I assume it can be used to define under which load the 0 p-state get's used.
Do you know a stress-utility which can generate stress in steps? Maybe sandras energy efficiency test shows a difference.

BTW I know Tcontrol is not the actual temp value in degrees but just an arbitrary value to represent it. That's why it's allowed to read subzero at high ambients.

It's like i expected. calibrated against the worst case temp with arbitrary scaling.
Looking at the MSR registers HTC seems to be an feature of future steppings.

What happened was, my first 9500 which is the main one I experimented highly with temps, it read the temp in BIOS the same as the physical Tcase temp most likely because it was missing the offset, but the ones after that were all different. This 9600BE reads the register properly (sub-ambients).

Same with F3xA4, I asked about it because on the NB register access it read 0b for me so I thought there's another way. It reads correctly now but many times it blanks out or reads F's.

In terms of temps i rely on the external sensor on the mobo. This one reports the highest temps. The avreage is +10° over CPU temp. A probe next to the prozessor reads the same temps as the cpu sensor most of the time, so i assume this temp is actualy higher.

Thanks for adding the bits, makes me not have to read the guide. Although you did make me read up the guide once again you know...

Skimmed over the whole thing one time, just to get an outline and know where to look for what. Alot of extra research is required on my side to read that doc.

[KTE]

kwark: AOD can do that, yup.

Achim: I'll check out those scripts when I get time. Been too busy yet.
Lowest I've had stable which is also my max stable yet (without freezes) is what I'm running since my last post.





Idle is still 94W but load is now lower. 186W P95 Small FFT.
Now typing in Firefox, 6 tabs open, with AV/FW engines running, AMD Power Mon and two text files open, I'm idling 96W AC.
P95/bench/firefox is all fine, just have to test a memory intensive game yet. First benchmark for L3 instability is EVEREST L3 bench. It will lock up if totally instable. The next best usually is rendering and better is a game. I've done some Apophysis fractal rendering fine. Next is a game.

It's been up for over 24hours so far without a problem. Problem for me is not P95 stability, that's quite easy. First 4 weeks 2.7GHz was 1.25V stable. The problem for me is avoiding the freeze after a day to three days idling. So far this is best yet. CPU seems to love low voltages over high ones.

Running 1.225VID because I can then access lower voltages below 1.264V but above 1.24V. Like right now Idle vs. Load =>

vs.

Yeah those p-states are great for tweaking, running with one HD and 3xFans atm.

CPU 2.6 (217x12) at 1.3V CPU VID
NB 2.17 (217x10) at 1.3V NB VID
MEM 578MHZ at 2.25V

idle: 157W AC
load: 270W AC

CPU .8 (217x4) at 1V CPU VID
NB 2.17 (217x10) at 1.3V NB VID
MEM 578MHZ at 2.25V

idle: 139W AC
load: 180W AC

Wow, big differences to mine and we're at similar MHz. Maybe it's the PSU efficiency giving those results? Actually you have 578 2.25V on MEM, and I have 536 2.16V. That's only maximum 3W DC more though. You also have a high HT ref. compared to mine (201) and my NB is low, 1.038 in P-State 1 and 1.038 in P-State 0. Previously max I've had stable at 1800MHz IMC was 1.050VID 1800 at 1.27V 2.7GHz CPU. I also run HT at 1.2V. It looks like I must be running lower current than you are, only that can explain the huge difference (almost 100W AC load).

These MSI BIOSes don't have VID options in BIOS (apart from old 1.13B).

Through testing I previously found, CnQ with low CPU VID/Voltage won't get much gains in dropping power compared to how much you gain by just dropping NB VID/Volts. I get quite a bit of gain by dropping NB VID/Volts, it is supposed to be a power hog which we knew since around June, and you can see that clearly. I have ran 2.211GHz max on 1.250VID NB stable so far, haven't tried more.

Make note: This was no way possible in first 3 weeks. 2GHz NB at 1.250V in them weeks would reboot.

Lowest possible consumption is cpu 200x4 at 0.9V nb 200x9 at 0.95V. In idle ~105W AC. So the board still needs more tweaking to beome more efficient.

A note aboute the NB multi. If CnQ is set to Auto in the Bios, the NB multi is always 9x. So it's required to up the ref HT to tune the nb.
However with above scripts it's possible to set the p-states and switch between em manual. Those work with CnQ disabled in bios.
A third p-state would be great, i'd like to have a low normal and high p-state.

If CnQ is disabled how do those scripts change between P-States and when?

Is 2.6GHz stable at 1.225V VID?

See above, yep. VCore is higher, 1.248V idle, 1.240V load. I'm surprised myself. 2.639GHz froze idling after 2 days at even 1.3-1.48VCore. I only recently started trying these lower volts.

The predefined p-states differ in the CPU DID and have the same CPU FID, can be it's faster to switch between the modes if only the DID changes.
NB DID must be equal on all cores's and p-states, no way to change the nb speed on the fly.

Yeah, I've switched CPU FID and DID with P-States and manually in Windows. But not NB DID/FID, no way as guide mentions.

Have you played with IddValue/IddDiv? I assume it can be used to define under which load the 0 p-state get's used.

I haven't, no. Is that register write enabled or only read? I thought it was auto set.

Do you know a stress-utility which can generate stress in steps? Maybe sandras energy efficiency test shows a difference.

I don't really. Only one I recall is Intel TAT which does this. You can always go old skool and use

int main()
{
    while (true);
}

...then just customize further and have four of them open to stress.

I'll tell you what I use though. I use this utility I've attached. Can choose to stress different cores with it (can set affinity manually to get different cores and different loads). Works good, not Prime95 load, because those iterations are FPU intensive and this isn't, but it produces a variety of load and priority is set to 4 (IIRC), so it won't jam your screen apps unusable. It's probably the first test I use each time. It still doesn't go up in steps though.

It's like i expected. calibrated against the worst case temp with arbitrary scaling.
Looking at the MSR registers HTC seems to be an feature of future steppings.

The real TCASE temp actually is the same as the TCONTROL value we get at one point near 60C according to graph given in BKDG. But what is funny is that TCONTROL is supposed to be lower all the way than the actual TCASE temp until a certain intersection point whereby TCONTROL becomes higher than the real TCASE temp (IHS temp). So you guys seeing high temps at some point under load but low temps idle get everything reported correctly.

In terms of temps i rely on the external sensor on the mobo. This one reports the highest temps. The avreage is +10° over CPU temp. A probe next to the prozessor reads the same temps as the cpu sensor most of the time, so i assume this temp is actually higher.

Yea true, Internal core temp will always be higher than TCASE temp (IHS). Usually minimum 15C higher.

Skimmed over the whole thing one time, just to get an outline and know where to look for what. Alot of extra research is required on my side to read that doc.

Hehe, you know the last guides were easier to read and make sense of than this one. I've heard many developers confused by this one and complain.