Intel's First Nehalem Cpu-Z Pic.

[tam2]

I will not comment any further.
but from what I know.
this comes from a good source.

Indeed
Link

-tam2-

[savantu]

This is more rubbish.

You've been more than corrected on the other forum you took this FUD too:

http://investorshub.advfn.com/boARDS...ge_id=26502149

Amazing ignorance.

Gee , I was told "Intel knows better" , not corrected.If you can't see the difference ,sorry for you.
I went there because I expected a reply from a specific person.

[fellix_bg]

AMD added L3 cache in K10 with the clear intention to cache-in the four core's interchange of data (following the basic of the MOESI protocol). Since K10 retains the very same approach implemented in the dual-core K8 part, that is: when a core (e.g. thread) needs a data from another one it must read it from the main memory (RAM), even if it is the L1 region. Of course, the requested data must be first flushed out to the RAM before the read-out.
The L3 cache in K10 is directly attached and controlled by the integrated North Bridge (a.k.a. IMC), so it is completely transparent for the any of the four cores -- none of them is "aware" that there is a big chunk of SRAM array between them and the main memory, but--on theory--the read/write latency reduction is definitely there, tightening the intercom cross-time. It is the NB task to manage the requests to the L3 properly.

Anyway, where comes Nehalem here. In the Core marchitecure, the cores are talking each other in a fully closed loop, e.g. the L1 caches of the two cores can interchange data directly between each other, and since the L2 cache is a shared commodity, the results of each core "doings" in there are instantly visible and available, without any need of flushing out.
Now, the advantage of this shared organization is diminishing when more cores are being added, creating more and more contention over the common interface (think about a shared telephone line). You see, the ideal model of an efficient multi-core architecture is, that each core should have its very own pool of fast and as-large-as-possible memory/cache, for its exclusive usage and control. That's good, but when it comes to interchanging data between the threads it creates a huge coherent contention -- the more the cores/threads are there, the exponential the overhead is! So, here it comes the idea of caching the cache - yet another level of fast memory, but this time available to anyone at equal base of access, and managed by a third party group (NB/IMC, just name it).
So, in a nutshell, adding another level of big cache allows for some cheap tricks, like reducing the size of the above (L1/L2) level and possibly making it even faster. In simple words -- it's all about finding the fragile balance between thread scaling efficiency, rapid data interchange and manageable cache size.

[R101]

And remember that the need for enormous ammounts of fast cache would be greatly diminished by tripple-channel IMC.

[fellix_bg]

The access parallelism (# of channels) or the interface width generally doesn't affect the read/write latency! It's good just for fast uniform streaming.

[BrownTown]

The access parallelism (# of channels) or the interface width generally doesn't affect the read/write latency! It's good just for fast uniform streaming.

yes, but the fact it is integrated now should provide lower latencies as well as the higher bandwidth.

[fellix_bg]

Yes, it should, but it will be still far off the on-die cache. Don't forget, that the memory banks are still very outside the CPU, on the MB.

[gallardo]

Contacted a buddy in D1D at Oregon about this SS and for what Nehalem info I could get out of him.

He says:
1) not a fake, but CPU-Z is off on several things (he won't tell exactly what)
2) Nehalem boots and runs stable under load on all major OSes
3) Intel could have it "rushed" to market in 2 months if need be, but they don't feel the competitive pressure to do so (thanks AMD).
4) most of what is being worked on now are the chipsets for the various platforms (desktop, server, etc.)



And yes Shintai, this is all on just my word. So don't bother thread crapping my post, time will prove one (or both of us) right.

That's all I need to know right now. If Intel has working samples that have passed quality control on most boards and it could rush it in 2 months... and with this in mind they say that it will be a lot better than Core and 30% more power efficient, I believe them. It will be better. The rest is just details. Intel does know better. And you know why? Because if you knew better, then you'd work for Intel... or at least be under NDA right now.

I trust the new Intel. Because we're talking about a new Intel. It makes perfect sense that they'll wait it out on Nehalem and just keep testing it and making it better before release. It's just common business sense. If they were to rush it now in 2 months and it would be buggy and it would have weak support, then I'd question Intel's management. I don't really need Nehalem right now so I don't mind waiting another year or so for it... as long as it's gonna be spot on and there won't be any incompatibilities.

[LyP0]

Intel does know better. And you know why? Because if you knew better, then you'd work for Intel... or at least be under NDA right now.

Dont forget one thing.
We want te make the best chip out there.
Intel wants to maken money.
That is, and will be their only goal.

[GMX]

it's not they're only goal, it's they're overall goal.

you don't make money doing a s**t job unless there is extremely crap/weak or no competition at all.

[KTE]

A shared L3 between 4 cores means highly complex arbitration mechanism ( that equals increased latency ).Look at AMD's K10 L3.Nothing to brag about either.It is slow , very slow.

Before you claim this, show me an L3 cache access/hit/success rate measurement saying it's slower than fetching data from RAM, adding overall latencies as you propose, or even if the L3 cache is at all slow.

As for the screenshot, it could be right or wrong. Guess work for all but a few. Most early stints are PR work for FUD and attention and wildly embellished but many do show the early preview of a product as below its true worth too.

And details are scarce on it at best. Speculation isn't going to interest me because IDK much actual facts from Intel or insiders about it yet and it's not slated for release till long away. Heck, even most of Penryn is not launched yet around most parts of the world. I don't believe Nehalem will be inferior to Penryn, these are processor engineers not some high school kids reading wikipedia or fudzilla and arguing about it; it will be an advancement and at least a margin better at lower voltages/power per core, especially with the cache algorithms, distribution, sizes employed and link widths, along with the IMC and the QPI. The problems and detriment to watch out for is the IMC+cache bonding, it can make it a winner or a loser. I hope the L2 cache isn't small though, quite honestly, it was Intel C2/Penryns major reliance and perf. booster over K8/K10. A very large L3 running equal or faster than the core speed itself though, can in itself remedy this situation for better multi-threaded performance, albeit still will suffer from slower single threaded perf... but two threads per app may very well remediate this situation too for an overall better core perf.

[JCornell]

screen of CPU-Z is fake imho.

i need real photo of real CPU with 1366 LGA pins.

exist only one photo:

Just because you don't have it, then y'all just jump to conclusion that it was fake ... I think this is the characteristic of XS members

This screen shot is originally mine ... Fxck to whom that steal my pics without permission !!


w/ QX9770




...

[DMH]

Hum really big CPU

[LowRun]

Just because you don't have it, then y'all just jump to conclusion that it was fake ... I think this is the characteristic of XS members

This screen shot is originally mine ... Fxck to whom that steal my pics without permission !!




...

You should watermark your pics, you would then know who when they surface on the web.

[Jowy Atreides]

is it me or are the pin contacts on the nehalem not round?

[DMH]

It's a shame that someone has stollen is pics but if they haven't then we wouldn't have seen the 2 others photo's he posted

[JCornell]

is it me or are the pin contacts on the nehalem not round?

Yeah, not round ...

[Jowy Atreides]

It's a shame that someone has stollen is pics but if they haven't then we wouldn't have seen the 2 others photo's he posted

I thought everyone had seen them already before this thread?

you can find them here - http://translate.google.com/translat...3Doff%26sa%3DG

Thanks JCornell

[Hornet331]

is it me or are the pin contacts on the nehalem not round?

yup not round, to increase the density.

[Zytek_Fan]

I want to see under the IHS!

[Periander6]

I wonder if Shintai is still claiming this is a sub 200 sqmm chip.

[frankR]

Nice screenies JC.

I want one... :drool:

This Nahalem isn't a monolithic quad?

You would like to think it is with the big L3 like Barcelona.

[ziddey]

The lands should have never been round. The pins on 775 boards also come up at an angle

[Monkeywoman]

thanks JC for the pics. i personally aren;t upgrading till penryn

[Shintai]

I wonder if Shintai is still claiming this is a sub 200 sqmm chip.

Because the package is bigger for more pins?

Open the IHS to find out