Nehalem Info from hkepc

[turtletrax]

You have to give it to Intel tho. Biggest change in transistor manufacture since the 60's in the 45nm parts, and then biggest change in core design since Pentium Pro.

AMD looks to be up the creek

[savantu]

Quite smug for someone whose own clock and IPC dreams were shattered a mere 3 months ago...

Owned.

Informal , this "joke" had a useful side too , it offered some real nitpicks from the people in the know , people who actually work at Oregon.

[informal]

You have to give it to Intel tho. Biggest change in transistor manufacture since the 60's in the 45nm parts, and then biggest change in core design since Pentium Pro.

AMD looks to be up the creek

45nm process from intel is impressive,but what biggest change in core design are you reffering to?
Nehalem is clearly using a baseline Penryn design while adding IMC(done before) and point-to-point I/O(also done before).The big change could be the GPU integration inside the MCM package(not integrated with the cores themselves,not at this stage).Ah yes,Hyper Threading is back also,but it takes small die area so it's nothing revolutionary or new.
Intel is basically catching AMD in the level of integration(IMC,DirectConnect) since this is needed at this point(not that intel couldn't make use of it before nehalem;they clearly didn't have CSI problems sorted out before this design or else they would use CSI with previous cores).

[Zytek_Fan]

That is why Nehalem has been called K10 + Penryn

[Shintai]

45nm process from intel is impressive,but what biggest change in core design are you reffering to?
Nehalem is clearly using a baseline Penryn design while adding IMC(done before) and point-to-point I/O(also done before).The big change could be the GPU integration inside the MCM package(not integrated with the cores themselves,not at this stage).Ah yes,Hyper Threading is back also,but it takes small die area so it's nothing revolutionary or new.
Intel is basically catching AMD in the level of integration(IMC,DirectConnect) since this is needed at this point(not that intel couldn't make use of it before nehalem;they clearly didn't have CSI problems sorted out before this design or else they would use CSI with previous cores).

Value Nehalem got GPU on die

Also PCIe is on die.

And AMD was catching up to Intel 20 years ago with IMC? 386SL anyone?

Unlike HT, CSI is actually designed right from the start. HT was not done well from the beginning and was overhelming bad for specially 8 socket setups. And I am not sure how good HT have been for the consumer market. It simply lacked the flexibility of the FSB type connected MCH. This is also one of my fears now for the future. I have a feeling we will be with DDR3 for a long long long time now.

[mesyn191]

And AMD was catching up to Intel 20 years ago with IMC? 386SL anyone?

There were plenty of chips before that too that used a IMC as well you know, its a old idea, AMD was just the 1st company to make a financially successful mass produced x86 chip with a IMC.

Unlike HT, CSI is actually designed right from the start. HT was not done well from the beginning and was overhelming bad for specially 8 socket setups.

Thats not a design flaw... the 8 socket Opteron systems were always for niche applications that had low bandwidth requirements and high CPU requirements. 4 socket Opteron systems were always supposed to be the "sweet" spot.

And I am not sure how good HT have been for the consumer market. It simply lacked the flexibility of the FSB type connected MCH.

Huh?! HT was/is about as flexible and open as you could get in the x86 CPU world. There were even 3rd party FPGA's/devices made by other companies for it!! What else could Intel's FSB connect to besides the MCH?

This is also one of my fears now for the future. I have a feeling we will be with DDR3 for a long long long time now.

Nah, still plenty of things they can do, just look at what Rambus has done with XDR.

Re: your ISA comments...

I expect we'll still be using x86/x86-64 chips 20 years from now, with various extensions to accommodate parallelization of course. Its not a very good ISA, but it gets the job done, and backwards compatibility is too valuable to get rid of. As for IA64 I don't think it'll ever enter a consumer grade chip, its strictly a "Big Iron" ISA that only has worthwhile advantages over x86 in FP code but is much more labor intensive to develop for. Strange that you dislike PPC even though its a better ISA than x86, what does it do wrong exactly?

[Shintai]

There were plenty of chips before that too that used a IMC as well you know, its a old idea, AMD was just the 1st company to make a financially successful mass produced x86 chip with a IMC.


Thats not a design flaw... the 8 socket Opteron systems were always for niche applications that had low bandwidth requirements and high CPU requirements. 4 socket Opteron systems were always supposed to be the "sweet" spot.


Huh?! HT was/is about as flexible and open as you could get in the x86 CPU world. There were even 3rd party FPGA's/devices made by other companies for it!! What else could Intel's FSB connect to besides the MCH?


Nah, still plenty of things they can do, just look at what Rambus has done with XDR.

Re: your ISA comments...

I expect we'll still be using x86/x86-64 chips 20 years from now, with various extensions to accommodate parallelization of course. Its not a very good ISA, but it gets the job done, and backwards compatibility is too valuable to get rid of. As for IA64 I don't think it'll ever enter a consumer grade chip, its strictly a "Big Iron" ISA that only has worthwhile advantages over x86 in FP code but is much more labor intensive to develop for. Strange that you dislike PPC even though its a better ISA than x86, what does it do wrong exactly?

I think you missed the point. Also are you telling me 386SL and 486SL wasnt mass produced?

HT/IMC or CSI/IMC is NOT flexible compared to the FSB solution. And the result is 939->AM2 and soon AM3 with complete memory change. AMD have been using Intel to push new memory types. Here is the catch, with Intel also having a IMC on each and every CPU. Who will make the jump? We will sit idle for along time due to the egg and the chicken issue. Who will make a new IMC on a CPU with a new socket without cheap memory? Who will make the cheap memory before the CPU on the new socket?

Ofcourse we will use x86/x64 20 years from now unless there is a radical change. PPC is newer than x86, but still just as flawed in design. The main problem and what will always dominate in a competitive IT industry is backwards compability. Everyone is so scared to make something new, because without compaiblity you go nowhere. Same reason our BIOSes still uses 16bit realmode, even tho we are in 2008 with 64bit and multicore CPUs. or that we today convert between CISC and RISC on CPUs.

And its perhaps even worse on the software side. Compability is whats holding us back everywhere.

Looking on IA64 and types like it. There is a large benefit in both size and power requirements due to the compiler based scheduling. Also its ability to scale with performance up to 11 issue wide (and maybe beyond) compared with your x86/x64 3/4 issue wide.

Now I am not saying IA64 is the golden grail. But I know for sure its not PPC/x86/x64. We simply just need to move on.

[gallardo]

Who will make the jump? We will sit idle for along time due to the egg and the chicken issue. Who will make a new IMC on a CPU with a new socket without cheap memory? Who will make the cheap memory before the CPU on the new socket?

Intel, obviously. They've got the bigger budget, they're the ones who pushed DDR2 and now DDR3 and PCI-express long before they were needed.

[Shintai]

Intel, obviously. They've got the bigger budget, they're the ones who pushed DDR2 and now DDR3 and PCI-express long before they were needed.

There is a massively huge difference.

Before you moved only a cheap chipset to support a new technology while you could use other chipsets for the cheap and known technology for you mass produced CPUs.

In near future you can only move if you move your entire platform at the same time. It would be like a Penryn CPU today only supporting DDR3.

In the past it was rather semi costless to make the change because it did not really effect the core business. But it will in the future and I think both AMD and Intel wont touch it due to risk and $$$.

[hollo]

that's not a big deal really. ddr2 was barely better than ddr. if i had my way AMD would have released 65nm k8s and a k8 MCM quad for socket 939, then shrunk them again to 45nm. those who want high memory bandwidth (gamers and other performance users) go out and buy ddr500 or ddr600 and do a little overclocking. no problem, and barely slower than ddr2 if slower at all. AMD following Intel into DDR2 so early was a business mistake imo (or at least, doing it at the expense of the socket 939 platform was a business mistake).

then switch to AM2/ddr2 for 45nm k10 and future architectures, and let Intel flounder with ddr2 or ddr3 or whatever, alone. but by backing Intel up on the ddr2 (and soon, ddr3) front AMD saved them from semi-repeating the rambus debacle.

and if ddr3 get's too slow... just add more channels, or use a NUMA style architecture (which microsoft windows and other software will take advantage of more and more efficiently as time goes on), or keep increasing the clockspeeds. because new memory standards really don't offer much performance improvement in real life apps, except in power consumption, and RAM power consumption is really really trivial (maybe with the exception of FB-DIMMS on servers with many gigabytes of memory, but again that's one of Intel's little experiments).

[JacKz5o]

DDR3 is too expensive

[mesyn191]

I think you missed the point. Also are you telling me 386SL and 486SL wasnt mass produced?

AMD was just the 1st company to make a financially successful mass produced x86 chip with a IMC

HT/IMC or CSI/IMC is NOT flexible compared to the FSB solution.

I don't think its a big deal that they won't be able to immediately switch to a new memory standard as soon as it becomes available as memory tech. tends to be slow to improve compared to CPU tech. Most new memory standards aren't very good in the beginning anyways vs. mature RAM from the previous standard. PC133 was better than DDR2100, DDR400 was better than DDR2 533, etc. and cheaper too. DRAM manufacturer's will just have more time to ramp production is all, which will hopefully reduce the "early adopters" tax, but I'm not optimistic about that...

And the result is 939->AM2 and soon AM3 with complete memory change.

I don't think socket changes much matter anymore as most enthusiasts don't keep the same mobo when they switch CPU's, and the avg. Joe Sixpack consumer just replaces the whole PC these days as they don't even know how to upgrade. Oh it would be nice to have 1 socket last for years like back in the socket 462 days, but I don't see it as a major loss.

AMD have been using Intel to push new memory types. Here is the catch, with Intel also having a IMC on each and every CPU. Who will make the jump? We will sit idle for along time due to the egg and the chicken issue. Who will make a new IMC on a CPU with a new socket without cheap memory? Who will make the cheap memory before the CPU on the new socket?

The DRAM producers and the chip companies will just coordinate changes more closely.

PPC is newer than x86, but still just as flawed in design.

Well, what do you think is so flawed about it? From what I've heard its a pretty decent ISA, nothing special mind you but nothing bad about it either.

The main problem and what will always dominate in a competitive IT industry is backwards compability. Everyone is so scared to make something new, because without compaiblity you go nowhere. Same reason our BIOSes still uses 16bit realmode, even tho we are in 2008 with 64bit and multicore CPUs. or that we today convert between CISC and RISC on CPUs.

AMD, Intel, IBM, etc. are after all just businesses, they're in it for the money and have to spend lots of it just to remain competitive, I think its reasonable if they want to play it safe.

Looking on IA64 and types like it. There is a large benefit in both size and power requirements due to the compiler based scheduling.

For FP code sure, for integer code not so much, and again its labor intensive vs. x86. Not as bad as developing for Cell from what I understand but still pretty tough... PC developers are having a hard enough time making ends meet right now as is, I don't think they can afford burden that IA64 would place on them.

Also its ability to scale with performance up to 11 issue wide (and maybe beyond) compared with your x86/x64 3/4 issue wide.

Getting that sort of ILP would be very difficult for most types of code from what I understand....

Now I am not saying IA64 is the golden grail. But I know for sure its not PPC/x86/x64. We simply just need to move on.

I dunno, I think AMD cleaned up x86 nicely with x86-64 and Intel made SSE2/3/4/etc. which allows you to get rid of x87 entirely, or at least relegate it to depreciated compatibility status. Parallel computing issues are pretty similar across all ISA's, and since this is the route AMD, Intel, and IBM are taking I'm not really so sure that we need a new ISA.

[mesyn191]

and if ddr3 get's too slow... just add more channels

This is expensive in terms of RAM (more modules required), socket/CPU costs (need LOTS more pins), and motherboard costs (more testing, tighter QC required, more PCB real estate gets used up, more layers, etc.). I think this is the main reason why only the server/enthusiast platform will have 3x channels of DDR3, and I expect it to be very expensive.

or use a NUMA style architecture

You need multiple CPU's or a MTH/external MCH's for NUMA IIRC. Expensive...

or keep increasing the clockspeeds.

This is the most likely route the DRAM producers will take, the other alternative is to make the bus wider but that means more pins, which requires more space and power, etc.

[hollo]

re: NUMA
i was thinking they could just stick two [dual channel?] memory controllers on a single CPU package and have a slightly NUMA style setup. like 4x4 packed into a single processor. but it might not be much use except for embarrassingly parallel workloads. raytracing might be among them, i'm not sure, so it could become more useful. it wouldn't be much use in most of today's applications, admittedly.

[sxs112]

Nehalem PIC

http://www.mobile01.com/topicdetail....3&last=4960456

[***Deimos***]

If all the rumours about nehalem are true then its going to mean some big changes:

3 memory channels on the high end. So, Corsair, Kingston, OCZ etc, will sell new triplet packs of memory? I mean if you buy two pairs, then you got extra spare?

Quad core - whats the big deal about it. And now with Hyperthreading? What are 95%+ of users suppsed to run to occupy 8 logical CPUs?

Different sockets for mainstream and high-end. Once again this will be odd for mobo makers, since you gotta design twice as many boards.
Similarly, will this mean different format heatsinks for the different sockets? Mobo compatibility issues?

Not backwards compatibliy. Well its kinda obvious. Its nice Intel lets us buy a P965 back in 2006, and use a quad core Penryn in 2008, but I guess these perks aren't guaranteed to last forever.

IPC - Ok, I've seen a lot of numbers thrown around. All the small apps that run in cache, obviously wont see impact from built in memory controller. Winrar benchmark or other bandwidth tests will continue to depend on bandwidth.. and the benefit few less cycles/ns by integration of memory controller are offset by Intel's large cache... ie bottom line you might see single digit gains in some apps.

Quad core + IGP + NB? Now seriously, do we really need huge monolithic system on a chip?

[Helmore]

Quad core + IGP + NB? Now seriously, do we really need huge monolithic system on a chip?

Who said anything about huge monolithic chips for their CPU+IGP solution?

[Blauhung]

Comments in red

If all the rumours about nehalem are true then its going to mean some big changes:

3 memory channels on the high end. So, Corsair, Kingston, OCZ etc, will sell new triplet packs of memory? I mean if you buy two pairs, then you got extra spare?

Yes, they will all most likely have 3 packs

Quad core - whats the big deal about it. And now with Hyperthreading? What are 95%+ of users suppsed to run to occupy 8 logical CPUs?

95% of the users will be getting the dual core with the IGP on die, so no worries. Those that do get the high end varriant, will probably also be those most likely to be using all the developing multithreaded software that has been slowly coming to market.

Different sockets for mainstream and high-end. Once again this will be odd for mobo makers, since you gotta design twice as many boards.
Similarly, will this mean different format heatsinks for the different sockets? Mobo compatibility issues?

I believe that since the sockets are very close in pin count, the heatsink mounting would be very easy to standardize. The only reason it isn't now for the desktop server break is because servers need the space and tend to use compact heasinks anyway.

Not backwards compatibliy. Well its kinda obvious. Its nice Intel lets us buy a P965 back in 2006, and use a quad core Penryn in 2008, but I guess these perks aren't guaranteed to last forever.

IMC is a huge boost, Plus, the 95% of people that get one, are going to get the whole thing pre assembled rather then upgrade a platform that at that point is more then 2 years old with a next gen CPU

IPC - Ok, I've seen a lot of numbers thrown around. All the small apps that run in cache, obviously wont see impact from built in memory controller. Winrar benchmark or other bandwidth tests will continue to depend on bandwidth.. and the benefit few less cycles/ns by integration of memory controller are offset by Intel's large cache... ie bottom line you might see single digit gains in some apps.

by similar arguments to that we should have only seen single digit gains when we moved from netburst to core. The reality was far different.

Quad core + IGP + NB? Now seriously, do we really need huge monolithic system on a chip?

Cheaper to make and market, makes it cheaper for everyone. Not to mention the hugely reduced latency between all the on die logic greatly boosting stock performance.

Who said anything about huge monolithic chips for their CPU+IGP solution?

oh, and yes, if anything, the integrated chips are smaller.

[dafeeessh]

time to start saving again