01/09/2008 BIOS
Q6600@422x8
G.Skill 2x2GB PC2 8000@1058MHz/5-5-3-15
XP SP3
Vista32 SP1
Vista64 SP1

All BIOS settings the same for all 3 operating systems with the
exception of tRFC. Vista32 required a value of 50 instead of 48.













XP SP3








Vista 32Bit SP1








Vista 64Bit SP1








Code:
CPU Feature Page
Thermal Management Control................Enabled
PPM (EIST) Mode...........................Enabled
Limit CPUID MaxVal........................Disabled
CIE Function..............................Auto
Execute Disable Bit.......................Enabled
Virtualization Technology.................Enabled
Core Multi-Processing.....................Enabled

Main BIOS Page
Exist Setup Shutdown......................Mode 2
Shutdown After AC Loss....................Disabled
O. C. Fail Retry Counter..................0
CLOCK VC0 Divider.........................Auto
CPU Clock Ratio...........................9x
CPU Clock.................................422 MHz
Boot Up Clock.............................Auto
DRAM Speed................................266/667
PCIE Clock................................100MHz
PCIE Slot Config..........................1X 1X

CPU Spread Spectrum.......................Disabled
PCIE Spread Spectrum......................Disabled
SATA Spread Spectrum......................Disabled

Voltage Setting Page 
CPU VID Control...........................Auto
CPU VID Special Add.......................111.10%
DRAM Voltage Control......................2.00V
SB 1.05V Voltage..........................1.070V
SB Core/CPU PLL Voltage...................1.55V
NB Core Voltage...........................1.37V
CPU VTT Voltage...........................1.35V
VCore Droop Control.......................Disnabled
Clockgen Voltage Control..................3.45V
GTL+ Buffers Strength.....................Strong
Host Slew Rate............................Weak
GTL REF Voltage Control...................Disabled
CPU GTL1/3 REF Volt.......................N/A
CPU GTL 0/2 REF Volt......................N/A
North Bridge GTL REF Volt ................N/A

DRAM Timing Page
Enhance Data Transmitting.................Fast
Enhance Addressing........................Fast
T2 Dispatch...............................Auto
Clock Setting Fine Delay..................Listed Below
CAS Latency Time (tCL)....................5
RAS# to CAS# Delay (tRCD).................5
RAS# Precharge (tRP)......................3
Precharge Delay (tRAS)....................15
All Precharge to Act......................4
REF to ACT Delay (tRFC)...................48
Performance Level.........................6
Read Delay Phase Adjust...................Listed Below
MCH ODT Latency...........................2
Write to PRE Delay (tWR)..................13
Rank Write to Read (tWTR).................11
ACT to ACT Delay (tRRD)...................3
Read to Write Delay (tRDWR)...............8
Ranks Write to Write (tWRWR)..............4
Ranks Read to Read (tRDRD)................5
Ranks Write to Read (tWRRD)...............4
Read CAS# Precharge (tRTP)................3
ALL PRE to Refresh........................3

Read Delay Phase Adjust Page
Channel 1 Phase 0 Pull-In.................Enabled
Channel 1 Phase 1 Pull-In.................Auto
Channel 1 Phase 2 Pull-In.................Auto
Channel 1 Phase 3 Pull-In.................Auto
Channel 1 Phase 4 Pull-In.................Auto

Channel 2 Phase 0 Pull-In.................Auto
Channel 2 Phase 1 Pull-In.................Auto
Channel 2 Phase 2 Pull-In.................Auto
Channel 2 Phase 3 Pull-In.................Auto
Channel 2 Phase 4 Pull-In.................Auto

Clock Setting Fine Delay Page
Ch1 Clock Crossing Setting................More Aggressive
DIMM 1 Clock fine delay...................Current 1312ps
DIMM 2 Clock fine delay...................Current 462ps
Ch 1 Command fine delay...................Current 862ps
CH 1 Control fine delay...................Current 400ps


Ch2 Clock Crossing Setting................More Aggressive
DIMM 3 Clock fine delay...................Current 1186ps
DIMM 4 Clock fine delay...................Current 374ps
Ch 2 Command fine delay...................Current 912ps
CH 2 Control fine delay...................Current 300ps

Ch1Ch2 CommonClock Setting................More Aggressive

Ch1 RDCAS GNT-Chip Delay..................Auto
Ch1 WRCAS GNT-Chip Delay..................Auto
Ch1 Command to CS Delay...................Auto

Ch2 RDCAS GNT-Chip Delay..................Auto
Ch2 WRCAS GNT-Chip Delay..................Auto
Ch2 Command to CS Delay...................Auto