DRAM Timing
- Enhance Data transmitting: FAST
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- Enhance Addressing: FAST
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- T2 Dispatch: Enabled
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Clock Setting Fine Delay
Ch1 Clock Crossing Setting: More Aggressive
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- DIMM 1 Clock fine delay: 6
- DIMM 2 Clock fine delay: 7
- Ch 1 Command fine delay: 11
- Ch 1 Control fine delay: 8
Ch2 Clock Crossing Setting: More Aggressive
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- DIMM 3 Clock fine delay: 6
- DIMM 4 Clock fine delay: 7
- Ch 2 Command fine delay: 11
- Ch 2 Control fine delay: 6
Ch1Ch2 CommonClock Setting: More Aggressive
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Ch1 RDCAS GNT-Chip Delay: Auto
Ch1 WRCAS GNT-Chip Delay: Auto
Ch1 Command to CS Delay: Auto
Ch2 RDCAS GNT-Chip Delay: Auto
Ch2 WRCAS GNT-Chip Delay: Auto
Ch2 Command to CS Delay: Auto (where cpuz sees 1T or 2T SETTING)
CAS Latency Time (tCL): 4
RAS# to CAS# Delay (tRCD): 4
RAS# Precharge (tRP): 4
Precharge Delay (tRAS): 5
All Precharge to Act: 4
REF to ACT Delay (tRFC): 30
Performance LVL (Read Delay) (tRD): 5
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Read delay phase adjust: Enter
Ch1 Read delay phase (4~0)
- Channel 1 Phase 0 Pull-In: AUTO
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- Channel 1 Phase 1 Pull-In: AUTO
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- Channel 1 Phase 2 Pull-In: AUTO
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- Channel 1 Phase 3 Pull-In: AUTO
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- Channel 1 Phase 4 Pull-In: AUTO
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Ch2 Read delay phase (4~0)
- Channel 2 Phase 0 Pull-In: Auto
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- Channel 2 Phase 1 Pull-In: Auto
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- Channel 2 Phase 2 Pull-In: AUTO
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- Channel 2 Phase 3 Pull-In: AUTO
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- Channel 2 Phase 4 Pull-In: AUTO
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