Official DFI LanParty UT X38-T2R(and LT) Discussion/Review/Overclock/Guide Thread

[eva2000]

i am hoping this gets resolved on future bios releases...i am a 1000 points behind what the IP35 Pro board will allow for 3D2001 bench...i faced the same going from abit's AB9 QuadGT (P965x) over to their P35 chipset...actually, it got better once i flashed the Pro's boot block...i see DFI has that switch incorporated in their autoexec.bat file....now, it's up to them to improve on (tweak) the performance output.

FIRST IMAGE IS THE IP35 PRO

SECOND IMAGE IS THE DFI LT X38 T2R

got everest bandwidth and latency comparisons between the 2 systems ? I'm finding from testing Gigabyte X38-DQ6 and DFI X38 LT that X38 by default seems to have loosened up some latencies to allow higher memory clocks but they've included in their respective bioses, options to tighten then back up. For DFI X38 those options seem to be these ones marked with *

It could be the case with most X38 boards compared to P35 ?

DRAM Timing
- Enhance Data transmitting: FAST *
- Enhance Addressing: FAST *
- T2 Dispatch: Enabled *

Clock Setting Fine Delay
Ch1 Clock Crossing Setting: More Aggressive *
- DIMM 1 Clock fine delay: 6
- DIMM 2 Clock fine delay: 7
- Ch 1 Command fine delay: 11
- Ch 1 Control fine delay: 8


Ch2 Clock Crossing Setting: More Aggressive *
- DIMM 3 Clock fine delay: 6
- DIMM 4 Clock fine delay: 7
- Ch 2 Command fine delay: 11
- Ch 2 Control fine delay: 6

Ch1Ch2 CommonClock Setting: More Aggressive *

Ch1 RDCAS GNT-Chip Delay: Auto
Ch1 WRCAS GNT-Chip Delay: Auto
Ch1 Command to CS Delay: Auto

Ch2 RDCAS GNT-Chip Delay: Auto
Ch2 WRCAS GNT-Chip Delay: Auto
Ch2 Command to CS Delay: Auto (where cpuz sees 1T or 2T SETTING)

CAS Latency Time (tCL): 4
RAS# to CAS# Delay (tRCD): 4
RAS# Precharge (tRP): 4
Precharge Delay (tRAS): 5
All Precharge to Act: 4
REF to ACT Delay (tRFC): 30
Performance LVL (Read Delay) (tRD): 5 *

Read delay phase adjust: Enter

Ch1 Read delay phase (4~0)
- Channel 1 Phase 0 Pull-In: AUTO *
- Channel 1 Phase 1 Pull-In: AUTO *
- Channel 1 Phase 2 Pull-In: AUTO *
- Channel 1 Phase 3 Pull-In: AUTO *
- Channel 1 Phase 4 Pull-In: AUTO *

Ch2 Read delay phase (4~0)
- Channel 2 Phase 0 Pull-In: Auto *
- Channel 2 Phase 1 Pull-In: Auto *
- Channel 2 Phase 2 Pull-In: AUTO *
- Channel 2 Phase 3 Pull-In: AUTO *
- Channel 2 Phase 4 Pull-In: AUTO *