NextGen VS. CurrentGen CPU: 3DMark06

[mstp2009]

awesome proof you got there

Reading comprehension is a B!tch isn't it?

[GoThr3k]

Reading comprehension is a B!tch isn't it?

http://www.xbitlabs.com/images/cpu/a...0/platform.jpg
http://www.septor.net/specs/amd/img/AMD8151BlockL.jpg
http://www.hothardware.com/articleim.../blockdiag.png

especially when memory doesnt have anything to do with hypertransport.....

doesnt look like the memory controller is connected with a hypertransport bus

[mstp2009]

http://www.xbitlabs.com/images/cpu/a...0/platform.jpg
http://www.septor.net/specs/amd/img/AMD8151BlockL.jpg
http://www.hothardware.com/articleim.../blockdiag.png

especially when memory doesnt have anything to do with hypertransport.....

doesnt look like the memory controller is connected with a hypertransport bus

GREAT!

That just makes my argument THAT MUCH STRONGER.


Core to core communication doesn't use HT either on 1 socket systems. So THERE GOES THAT THEORY.
If the memory bus isn't sharing HT bandwidth, then that what ON EARTH do you possibly expect to consume >12.8GB/s of bandwidth?

[GoThr3k]

GREAT!

That just makes my argument THAT MUCH STRONGER.


Core to core communication doesn't use HT either on 1 socket systems. So THERE GOES THAT THEORY.
If the memory bus isn't sharing HT bandwidth, then that what ON EARTH do you possibly expect to consume >12.8GB/s of bandwidth?

haha,first you are providing proof
proof isnt correct at all,know you say it confirms that your proof is right

[Kingcarcas]

Are there genuine gripes here or are people just mad AMD is getting smoked?

[mstp2009]

haha,first you are providing proof
proof isnt correct at all,know you say it confirms that your proof is right

Still waiting on YOUR proof that HT2/3 is needed to overcome some mythological bottleneck.


I'll HAPPILY admit that having the memory bus on the HT bus was an error on MY PART. But still doesn't INVALIDATE the point that on a SINGLE SOCKET SYSTEM, there is bandwidth to spare on the HT bus.

That is the SINGLE POINT you have trouble grasping (that poor reading comprehension thing again - bites you in the arse every time).

[mstp2009]

Are there genuine gripes here or are people just mad AMD is getting smoked?

I'm pissed, for one, that K10 only comes up to par with an architecture that has been out 16 months now. It means we are all going to get d!cked over at the cash register when we buy high-end equipment.

GoThr3k just has this unfounded idea that HT3 is magically going to make K10 a faster CPU. HT3 doesn't do SQUAT unless you are in a multi-socket system.

[generics_user]

I'm pissed, for one, that K10 only comes up to par with an architecture that has been out 16 months now. It means we are all going to get d!cked over at the cash register when we buy high-end equipment.

GoThr3k just has this unfounded idea that HT3 is magically going to make K10 a faster CPU. HT3 doesn't do SQUAT unless you are in a multi-socket system.

QFT

however NB speed in K10 has a HUGE impact on performance and if i understand it correctly ht link speed + NB speed is the same on HT3 the HT link speed does have a significant impact on performance with K10 (not due to limited I/O bandwidth more due to a higher NB+L3 frequency -> more effective prefetchers and lower latency L3 cache

[mstp2009]

QFT

however NB speed in K10 has a HUGE impact on performance and if i understand it correctly ht link speed + NB speed is the same on HT3 the HT link speed does have a significant impact on performance with K10 (not due to limited I/O bandwidth more due to a higher NB+L3 frequency -> more effective prefetchers and lower latency L3 cache

Interesting on the lower latency. Can you link me where you read that?

[justapost]

Split power planes. Feeding the memory controller and the core from different power rails is not a direct improvement to the memory subsystem, but it does allow the memory controller to be clocked higher than the CPU core.

Link
So modifying the NB speed is more an energy efficiency thing than an OC feature.

[generics_user]

Interesting on the lower latency. Can you link me where you read that?

Kyosens latency (1800mhz)
some more posts ago this user said that his IMC runs at 1400 mhz-note the higher latency

and as we know K10 IMC speed = NB speed

[generics_user]

Link
So modifying the NB speed is more an energy efficiency thing than an OC feature.

not really, NB SPEED = L3 speed...

[nemrod]

BIOS have no option to change NB FID.The ES is 8x,so if the 200MHz FSB,NB Core speed only have 1600MHz Option.

some guy does not want to see the ES which can OC 3GHz, so let me do another test with the 9600/9500 retail.....

I'm sorry for you that you provide some long waiting results and that some people just complain they are not like they have dream.
Thank you anyway for your work

[nemrod]

The only question I want answered. Who is this guy with the engineering sample so blatantly able to break his NDA?

Why, you'd prefer to have only inquirer informations?

[mstp2009]

NB communicates to the CPU via HT, it's been this way since HT1.

But the L3 talks to memory, not the NB.

Sure you aren't looking at memory latency? Those latencies are horrible for a cache (even L3).

EDIT - I was referring to the first link which talks about ns time, fyi. The second one clearly shows cycles (which at 52 cycles is not pretty also).

[Hornet331]

mstp2009 lets wait for the 19th/20th i think then there is plenty of information available to discuss stuff like this.

[generics_user]

NB communicates to the CPU via HT, it's been this way since HT1.

But the L3 talks to memory, not the NB.

Sure you aren't looking at memory latency? Those latencies are horrible for a cache (even L3).

EDIT - I was referring to the first link which talks about ns time, fyi. The second one clearly shows cycles (which at 52 cycles is not pretty also).

kyosen got 43 cycles with 1800 mhz on the L3 cache:

kyosen's screenie

still not pretty but it shows what i mean

[justapost]

BIOS have no option to change NB FID.The ES is 8x,so if the 200MHz FSB,NB Core speed only have 1600MHz Option.

Ah, ok it was not mentioned in the article what stock clock the phenom has. Thank you for the clarification.

not really, NB SPEED = L3 speed...

Ok, from an extreme perspective that has an impact.
I thought about a more efficient memory sytem at lower cpu clocks.

[GoThr3k]

I'm pissed, for one, that K10 only comes up to par with an architecture that has been out 16 months now. It means we are all going to get d!cked over at the cash register when we buy high-end equipment.

GoThr3k just has this unfounded idea that HT3 is magically going to make K10 a faster CPU. HT3 doesn't do SQUAT unless you are in a multi-socket system.

HT3 will do nothing much for K10 (in single socket systems) i have never stated otherwise
maybe 1-2%,but that me be recognised as statistical error

[mstp2009]

HT3 will do nothing much for K10 (in single socket systems) i have never stated otherwise
maybe 1-2%,but that me be recognised as statistical error

AGREED.

The cycle change in latency b/w the two users listed above is VERY interesting. I didn't check, but were they the same stepping of K10?

43 cycles, however, is still play ugly.

[madcho]

HT3 will do nothing much for K10 (in single socket systems) i have never stated otherwise
maybe 1-2%,but that me be recognised as statistical error

yes HT 3.0 is not so usefull for single socket, but don't forget, HT 3.0 motherboards come with split plane, and increase the memory controler frequency.

AGREED.

The cycle change in latency b/w the two users listed above is VERY interesting. I didn't check, but were they the same stepping of K10?

43 cycles, however, is still play ugly.

It's a new serial cache. It's a bit different from old cache but it's as fast even the high cycles latency.

Brisbane use the same cache for L2 ( K10 for L3 ). It's high latency but it's as fast.

[generics_user]

AGREED.

The cycle change in latency b/w the two users listed above is VERY interesting. I didn't check, but were they the same stepping of K10?

43 cycles, however, is still play ugly.

both B1 check cpu-z screens.

as L3 cache seems to handle cache traffic between the cores (L2) and serves as a buffer between the CPU and the IMCs there should be some more % achieveable by increasing NB freq...

and we still don't know if the IMC runs in ganged or unganged mode (unganged allows the IMC to write and read at the same time opposed to read/write only in old K8 IMC, at least that's how i understand it after reading kyosens thread), if the IMC runs ganged there is a chance that K10 can get a higher IPC than yorkfield (but i don't count on it )

[mstp2009]

both B1 check cpu-z screens.

as L3 cache seems to handle cache traffic between the cores (L2) and serves as a buffer between the CPU and the IMCs there should be some more % achieveable by increasing NB freq...

and we still don't know if the IMC runs in ganged or unganged mode (unganged allows the IMC to write and read at the same time opposed to read/write only in old K8 IMC, at least that's how i understand it after reading kyosens thread), if the IMC runs ganged there is a chance that K10 can get a higher IPC than yorkfield (but i don't count on it )

IIRC doesn't the L3 cache and IMC scale their MHz/GHz speed differently depending on the CPU multiplier and the relative frequencies of the cores?

There was some complex BS going on w/ K10 that made it pretty decent (on par w/ C2Q) at certain frequencies, and absolutely SUX at others.

[expreview]

I will show you guy the Retail version test with GP9600, like Cinebench score will announce soon.

you would know about the Phenom default performance.....

[tictac]

I will show you guy the Retail version test with GP9600, like Cinebench score will announce soon.

you would know about the Phenom default performance.....

the new CPU-Z Version can show NB speed and correct memory speed and timing...

here...version CPU-Z Version 1.41.4 preview