Power consumption increases with the square of V.
Intel's 45nm offers both : high frequency and low powerTheres only two ways to take for CPU design when it comes to metal gate AFAIK and ones for high performance/high TDP and the other is for low TDP/v.low standby TDP preference. Intel chose the high-k dielectric metal gate which means you get maximum clock speeds (makes for easy PR work too) and not much TDP advantage over what the basic node offers
http://www.techreport.com/articles.x/13470/15
What should be noted is : process improvements offer lower power consumption at the same freq or higher freq at the same power.
Metal gates drastically reduce the biggest factor in leakage once you go under 65nm.
That's utter BS.SOI and metal gates address different factors of leakage , SOI is becoming less useful once you get to 65nm and lower.
and AMD AFAIK chose low-k dielectric along with IBM, which is not made for high clocks at all but low power usage. SOI and other straining techniques combined can do better than having a metal gate BTW.
The fact that SOI doesn't adress gate leakage , the biggest problem at 65/45/32nm means that AMD had to use thicker gates which equal slower transistors.
So basically , you say something and then deny it ?Then again I read AMD chose to go for high-k dielectric metal gate at 32nm, so I'm not sure what they're doing for 45nm or 32nm anymore. You can read more accurate info here: http://www.semiconductor.net/article/CA6402509.html
Huh ? Where do you get this info ?Around 1.5V is about the max possible a CPU MFG wants to retail at, and usually never above 1.4V nowadays. I wonder what the TDP is. Intel breaks the 130W barrier after 3GHz on Penryn at 1.216-1.248V, so what would 1.536V 3GHz quad get? Must be high but they're planning to retail 2.8GHz this year, so we'll see what they have to offer then.
1.5V is huge for a 65nm process ; 90nm used 1.35-1.4V.
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