K10 Scores starting to surface

[nn_step]

Gateway fore one is buying
http://www.techpowerup.com/index.php?39579

of course given the significant advantage that they provide in the most lucrative market right now (virtualization, where people are paying up to 6 times more for performance compared to regular high end servers)

[PhilDoc]

So the two reviews that show it not coming up to scratch are sub standard?

As Dr Evil would say... riiiiight

You may want to read the Anand Quad article again. On average a Barcelona running at 2G equated to a Xeon running at 2.25G and that was running two benches that highly favor Intel. Take those out and it equates to one running at a little less then 2.4G. That's a 20% increase

As far as Gateway selling them, I expect most manufatures to offer them in the near future. I saw one article were someone bought 15,000 of them to build a super computer, lol. It'd be fun to be part of that, lol

[dave_graham]

gateway, dell, sun, hp, ibm are all the Tier One vendors who will be selling quad boxes (well, gateway....whatever)

Boxx, Appro, et al. would be Tier Two's that will be carrying them as well.

*shrug*

not worried about commercial/enterprise acceptance, personally.

dave

[gundersausage]

You may want to read the Anand Quad article again. On average a Barcelona running at 2G equated to a Xeon running at 2.25G and that was running two benches that highly favor Intel. Take those out and it equates to one running at a little less then 2.4G. That's a 20% increase

Yeah I can tell you were all blown away by your defensive posts

[metro.cl]

Uberman,some of us have to work ,you know .Why you ask?

I do have a few words to say and i must say i am really pleased with K10.It does very well in current platform,and does that at low frequencies and with a low power usage too(this is great news for those planing to swap RevF with K10).Also,i am a bit surprised about the "reviews"(both anand and tech report are sub standard ones-probably due to time issues) which used the B1,but i guess AMD knows what they are doing.BA is the launch stepping,so i expect the reviews with them hitting the net around the end of the month.
AMD finally have quad core in the most needed sector and they have a really good and promising one.With clocks up to 2.6Ghz for server parts at the end of the year,there should be some really interesting reviews coming up(by that time,the whole platform/BIOS issue will be done with).

I would like to know about this more, is current TDP for K10 considering all the new power saving features? if so what is the TDP of a upgrade on a mobo that doesnt support all new power savings?

[PhilDoc]

Yeah I can tell you were all blown away by your defensive posts

You lost me, I'm just reading the article, poor as it is. I have no investment in AMD. I don't own any AMD stock and I don't think of my computer as an extension of my penis ( I don't take this personally). Do I want them to do well, certainly, we all should. If they do well we all get faster cpus and great prices.

I understand that you're young, but instead of trying to taunt someone into a flame war, why not read the articles and give some intellegent input.

[gundersausage]

You lost me, I'm just reading the article, poor as it is. I have no investment in AMD. I don't own any AMD stock and I don't think of my computer as an extension of my penis ( I don't take this personally). Do I want them to do well, certainly, we all should. If they do well we all get faster cpus and great prices.

I understand that you're young, but instead of trying to taunt someone into a flame war, why not read the articles and give some intellegent input.

I read them and came to a different conclusion, so take your own advice and stop taking it personally.. and assuming you know my age is embarrassingly ignorant and compromises your entire little "no investment" diatribe

[dave_graham]

I would like to know about this more, is current TDP for K10 considering all the new power saving features? if so what is the TDP of a upgrade on a mobo that doesnt support all new power savings?

i'll have to see.

AMD still quotes ACP at 75w for 95W parts on single plane boards....so, i think we can easily replicate this.

I'm looking to get a S3992-E in within the next two weeks and compare it to the 3992 (single plane) i have now. will test with BA chips on that (to keep things consistent, etc.

cheers,

dave

[KTE]

Yea low fetch latencies keep the processor fed with data quicker in all processors, and in Techreports review it showed the L3 latency playing a significant part and being reduced quite a bit as the clocks are ramped up - exactly what AMD has been saying for a while. It's dependent on the Northbridge frequency.

I am certain K10 L1 victim cache + L3 cache is like L1+L2 cache of Core 2 with respect to performance. If we had a way to disable a QX6850 cache from 512MB x2 to 4MB x2, we'd see how the L2 cache impacts Core 2 performance and latencies.

a.) coherent dual HT links for inter-processor communication (which has not realistically benchmarked)

Because of cache coherent HT (globally addressable memory address space), 1 Opteron in dual channel has 10,700MB/s peak theoretical bandwidth at DDR2-667 whereas 4 have 42,800MB/s.. correct?

From all May 06-July 07 discussions, I recall K10 was to have 4 HT links but that only 3 were to work in 2007 until DCA 2.0 and HT 3.0 is implemented. I specifically recall David Kanter mentioning first launch K10 having 4 HT 1.1 links and one used specifically for I/O in the multi-socket environment which avoids multi-hop snoop traffic. Is this still the case?

So is it supposed to be 3 16-bit ccHT 1.1 links in total for K10?

[dave_graham]

Because of cache coherent HT (globally addressable memory address space), 1 Opteron in dual channel has 10,700MB/s peak theoretical bandwidth at DDR2-667 whereas 4 have 42,800MB/s.. correct?

sorry...I misspoke about this.

interprocessor communication (for dual HT link boards) has 1 coherent and 1 additional non-coherent link. so, basically traffic can now be routed two different ways...should offload some of the menial requests..I'm asking for more information on this (as well as testing procedures to accurately show this).

From all May 06-July 07 discussions, I recall K10 was to have 4 HT links but that only 3 were to work in 2007 until DCA 2.0 and HT 3.0 is implemented. I specifically recall David Kanter mentioning first launch K10 having 4 HT 1.1 links and one used specifically for I/O in the multi-socket environment which avoids multi-hop snoop traffic. Is this still the case?

So is it supposed to be 3 16-bit ccHT 1.1 links in total for K10?

iirc, it's 2 coherent 16bit links and 1 16-bit HT link. so, 1 coherent p-to-p, 1 p-to-p, and 1 system. 8000s should have 4, iirc.

i'll need to go back and research this a bit more.

cheers,

dave

[PhilDoc]

I read them and came to a different conclusion, so take your own advice and stop taking it personally.. and assuming you know my age is embarrassingly ignorant and compromises your entire little "no investment" diatribe

Well this is not my field, but after 15yrs of education I think I do alright. As far as assuming your age, I'm just going by your comments. Either way, I give up, tried to show you why people have been irritated by your posts (which has nothing to do with you thinking that Barcelona is a flop), but you insist on trying to start a flame war. So flame on, I have better things to do.

[Dresdenboy]

I would like to know about this more, is current TDP for K10 considering all the new power saving features? if so what is the TDP of a upgrade on a mobo that doesnt support all new power savings?

On boards, which don't provide separate voltages, K10 would run the internal NB at the same voltage as the cores but a lower NB clock (than on an F1207+ MB) to still fit into the TDP limit.

[gundersausage]

Well this is not my field, but after 15yrs of education I think I do alright. As far as assuming your age, I'm just going by your comments. Either way, I give up, tried to show you why people have been irritated by your posts (which has nothing to do with you thinking that Barcelona is a flop), but you insist on trying to start a flame war. So flame on, I have better things to do.

I'm not the least bit interested in a flame war and those that are "not invested" recognize that.. I've even had an apology from one of you who admitted he was a bit sensitive after seeing the results.. so spare me the 15 years of education.. I'm well aware that everybody on the internet is a well endowed genius supermodel

The truth is if you believed half of what you say you wouldn't bother trying to "educate me"

As the old saying goes: Methinks he doth protest too much

[metro.cl]

On boards, which don't provide separate voltages, K10 would run the internal NB at the same voltage as the cores but a lower NB clock (than on an F1207+ MB) to still fit into the TDP limit.

that means lower performance? how lower?

[LIKMARK]

that means lower performance? how lower?

That means lower memory bandwidth I think.

[dave_graham]

the MC is clocked 400mhz lower than core frequency on 2350s with a single plane power arrangement.

the MC is clocked 200mhz lower than core frequency on 2350s with a split plane power arrangement.

that can definitely impact bandwidth.

dave

[dave_graham]

*Why was HwP disabled? Is there a problem with it or what?

HW prefetching was disabled because it can significantly impact the performance of those Intel processors on specjjbb.

dave

[informal]

Some BIOS support news:

General Software, Inc. First BIOS Provider to Support AMD Barcelona Processor
11 Sep 07 17:07

SEATTLE, WA -- (MARKET WIRE) -- 09/11/07 --

General Software, Inc. is the first BIOS provider to offer commercially readyfirmware for AMD's (NYSE: AMD) new Quad-Core AMD Opteron(TM) processor. Released in conjunction with yesterday's launch of Barcelona, General Software' Embedded BIOS(R) with StrongFrame(TM) Technology firmware is also the first to leverage AMD's new AGESA 3 software. The newest version of AMD's AGESA is required to enable all four processors on a single core.

As the silicon industry continues to leap ahead and computing environments get more and more complex, General Software remains the leader in firmware innovations that unleash the power of CPU advances for the market benefit of OEMs and ODMs. A long-term AMD (http://www.amd.com/us-en/ ) partner, General Software gained early access to AMD's Quad-Core Opteron hardware and worked in concert with AMD to ensure optimal performance for mutual customers.

The Quad-Core AMD Opteron(TM) processor that was announced yesterday comprises four processing cores on a single piece of silicon. AMD bills it as "the world's most advanced x86 processor ever designed and manufactured and the first native x86 quad-core microprocessor" delivering"dramatically escalating performance-per-watt emphasis."

General Software provides firmware for a wide range of applications including telecom/datacom equipment, servers, blades, Ultra-Mobile PCs, industrial PCs, targeted PCs, differentiated mainboards, and embedded devices including medical, gaming, kiosks, point-of-sale, DVR and commercial and military avionics.

Embedded BIOS(R) with StrongFrame(TM) Technology, already running some of the world's largest high performance data centers, increases performance and reliability whilereducing support costs with proprietary features such as:

-- a High Availability (HA) subsystem that monitors entire system health
and "self heals" itself by implementing configurable recovery policies,
-- remote provisioning and monitoring,
-- the fastest boot in the industry (0.085 second POST, 0.838 second
Linux boot, and 24 second Windows Vista boot),
-- a robust set of diagnostics, and
-- advanced security options.
"General Software has consistently demonstrated its ability to support the
latest silicon and technologies that drive industry innovation and enable OEMs
to achieve faster time-to-market at lowered costs," said Craig Husa,General
Software CEO. "The Quad-Core AMD Opteron processor answers the callfor rugged
and high-performance, high-demand computing required by large enterprises and
intense computing requirements," continued Husa.

General Software recently unveiled its flagship StrongFrame(TM) Technology, which enables targeted cores to be created for a wide range of applications. Unlike other firmware offerings, which have a centralized proprietary core and architectural modules for CPUs, chipsets, and other components underneath it, StrongFrame(TM) Technology allows the core itself to be a pluggablemodule, enabling many cores to be supported within the same framework. Theindividual cores then target specific markets, such as telecom, servers, UMPCs, targeted PCs, and embedded.

StrongFrame(TM) Technology then leverages proprietary programming of CPUs, chipsets, SIOs, whole boards, and other building blocks across all General Software's specialized cores. The result is that the same set of silicon programming modules can be used across many unique applications.

With StrongFrame(TM) Technology, OEMs can quickly produce and differentiatemotherboards for multiple markets, saving money and time otherwise spent onhaving to independently build firmware for each of their markets.

About General Software, Inc.

http://www.nyse.com/interface/jsp/NH...dowjones=false

[Kayin]

Just wondering,

I'm really looking hard at a Barcelona system to replace my desktop and do some other tasks with, and I'm looking really hard at the MSI K9ND Speedster board, for extra RAM support and the ability to run unbuffered RAM (proven on their forums), is there going to be a BIOS for this board, or any good reason they wouldn't be a good match? If not, I'll probably get the Tyan and call it a day (no ASUS for me, thanks.)

[KTE]

sorry...I misspoke about this.

interprocessor communication (for dual HT link boards) has 1 coherent and 1 additional non-coherent link. so, basically traffic can now be routed two different ways...should offload some of the menial requests..I'm asking for more information on this (as well as testing procedures to accurately show this).

Ah right, thanks. There was A LOT of speculation about all this, especially in programmers and HPC markets. Don't you think the performance impact with HT coherency will be very software coding dependent though?

In July 2007, seriously, reading around, there weren't many professional coders who understood how to optimize for this hardware capability in K10 at the 4S and above stage.

iirc, it's 2 coherent 16bit links and 1 16-bit HT link. so, 1 coherent p-to-p, 1 p-to-p, and 1 system. 8000s should have 4, iirc.

i'll need to go back and research this a bit more.

Thanks again Dave. I hope we could enable and disable these links and their coherency manually, and get a 4S board to use 2x 2300 series and 2x 8300 or something similar. (AFAIK ATM it's hardware controlled through the chip 4 bit license register from the factory though, aswell as the pin connection)

But that would then destroy the +2x higher market pricing on the 4-way+ chips, so mp firms won't do it.

[tictac]

Some BIOS support news:

http://www.nyse.com/interface/jsp/NH...dowjones=false

WOW!!! Thanks

[informal]

Yeah,i especially like this quote :

-- the fastest boot in the industry (0.085 second POST, 0.838 second
Linux boot, and 24 second Windows Vista boot)

[dave_graham]

Just wondering,

I'm really looking hard at a Barcelona system to replace my desktop and do some other tasks with, and I'm looking really hard at the MSI K9ND Speedster board, for extra RAM support and the ability to run unbuffered RAM (proven on their forums), is there going to be a BIOS for this board, or any good reason they wouldn't be a good match? If not, I'll probably get the Tyan and call it a day (no ASUS for me, thanks.)

you need a dual HT/dual power plane board to really take advantage of the platform.

the K9ND doesn't support that right now.

hold out for Tyan.

dave

[dave_graham]

Ah right, thanks. There was A LOT of speculation about all this, especially in programmers and HPC markets. Don't you think the performance impact with HT coherency will be very software coding dependent though?

yes but that also depends on the mechanisms in place for routing traffic to begin with....chicken and the egg conundrum, really.

In July 2007, seriously, reading around, there weren't many professional coders who understood how to optimize for this hardware capability in K10 at the 4S and above stage.

yeah, if there were really good "aware" compilers, that might help but..we'll see. It's good to see AMD actually taking the bull by the horns (as it were) by being proactive with optimizations for compiling (extra SSE5 instructions, etc.)

Thanks again Dave. I hope we could enable and disable these links and their coherency manually, and get a 4S board to use 2x 2300 series and 2x 8300 or something similar. (AFAIK ATM it's hardware controlled through the chip 4 bit license register from the factory though, aswell as the pin connection)

But that would then destroy the +2x higher market pricing on the 4-way+ chips, so mp firms won't do it.

meh...the real news is that the HT3 clock gen is already on the core.

cheers,

dave

[Lewis_UK]

I cant wait to see some competion against the Core 2's