Yea low fetch latencies keep the processor fed with data quicker in all processors, and in Techreports review it showed the L3 latency playing a significant part and being reduced quite a bit as the clocks are ramped up - exactly what AMD has been saying for a while. It's dependent on the Northbridge frequency.

I am certain K10 L1 victim cache + L3 cache is like L1+L2 cache of Core 2 with respect to performance. If we had a way to disable a QX6850 cache from 512MB x2 to 4MB x2, we'd see how the L2 cache impacts Core 2 performance and latencies.

Quote Originally Posted by dave_graham View Post
a.) coherent dual HT links for inter-processor communication (which has not realistically benchmarked)
Because of cache coherent HT (globally addressable memory address space), 1 Opteron in dual channel has 10,700MB/s peak theoretical bandwidth at DDR2-667 whereas 4 have 42,800MB/s.. correct?

From all May 06-July 07 discussions, I recall K10 was to have 4 HT links but that only 3 were to work in 2007 until DCA 2.0 and HT 3.0 is implemented. I specifically recall David Kanter mentioning first launch K10 having 4 HT 1.1 links and one used specifically for I/O in the multi-socket environment which avoids multi-hop snoop traffic. Is this still the case?

So is it supposed to be 3 16-bit ccHT 1.1 links in total for K10?