Quote Originally Posted by dave_graham View Post
sorry...I misspoke about this.

interprocessor communication (for dual HT link boards) has 1 coherent and 1 additional non-coherent link. so, basically traffic can now be routed two different ways...should offload some of the menial requests..I'm asking for more information on this (as well as testing procedures to accurately show this).
Ah right, thanks. There was A LOT of speculation about all this, especially in programmers and HPC markets. Don't you think the performance impact with HT coherency will be very software coding dependent though?

In July 2007, seriously, reading around, there weren't many professional coders who understood how to optimize for this hardware capability in K10 at the 4S and above stage.

iirc, it's 2 coherent 16bit links and 1 16-bit HT link. so, 1 coherent p-to-p, 1 p-to-p, and 1 system. 8000s should have 4, iirc.

i'll need to go back and research this a bit more.
Thanks again Dave. I hope we could enable and disable these links and their coherency manually, and get a 4S board to use 2x 2300 series and 2x 8300 or something similar. (AFAIK ATM it's hardware controlled through the chip 4 bit license register from the factory though, aswell as the pin connection)

But that would then destroy the +2x higher market pricing on the 4-way+ chips, so mp firms won't do it.