K10 Scores starting to surface

[dave_graham]

Because of cache coherent HT (globally addressable memory address space), 1 Opteron in dual channel has 10,700MB/s peak theoretical bandwidth at DDR2-667 whereas 4 have 42,800MB/s.. correct?

sorry...I misspoke about this.

interprocessor communication (for dual HT link boards) has 1 coherent and 1 additional non-coherent link. so, basically traffic can now be routed two different ways...should offload some of the menial requests..I'm asking for more information on this (as well as testing procedures to accurately show this).

From all May 06-July 07 discussions, I recall K10 was to have 4 HT links but that only 3 were to work in 2007 until DCA 2.0 and HT 3.0 is implemented. I specifically recall David Kanter mentioning first launch K10 having 4 HT 1.1 links and one used specifically for I/O in the multi-socket environment which avoids multi-hop snoop traffic. Is this still the case?

So is it supposed to be 3 16-bit ccHT 1.1 links in total for K10?

iirc, it's 2 coherent 16bit links and 1 16-bit HT link. so, 1 coherent p-to-p, 1 p-to-p, and 1 system. 8000s should have 4, iirc.

i'll need to go back and research this a bit more.

cheers,

dave

[KTE]

sorry...I misspoke about this.

interprocessor communication (for dual HT link boards) has 1 coherent and 1 additional non-coherent link. so, basically traffic can now be routed two different ways...should offload some of the menial requests..I'm asking for more information on this (as well as testing procedures to accurately show this).

Ah right, thanks. There was A LOT of speculation about all this, especially in programmers and HPC markets. Don't you think the performance impact with HT coherency will be very software coding dependent though?

In July 2007, seriously, reading around, there weren't many professional coders who understood how to optimize for this hardware capability in K10 at the 4S and above stage.

iirc, it's 2 coherent 16bit links and 1 16-bit HT link. so, 1 coherent p-to-p, 1 p-to-p, and 1 system. 8000s should have 4, iirc.

i'll need to go back and research this a bit more.

Thanks again Dave. I hope we could enable and disable these links and their coherency manually, and get a 4S board to use 2x 2300 series and 2x 8300 or something similar. (AFAIK ATM it's hardware controlled through the chip 4 bit license register from the factory though, aswell as the pin connection)

But that would then destroy the +2x higher market pricing on the 4-way+ chips, so mp firms won't do it.

[dave_graham]

Ah right, thanks. There was A LOT of speculation about all this, especially in programmers and HPC markets. Don't you think the performance impact with HT coherency will be very software coding dependent though?

yes but that also depends on the mechanisms in place for routing traffic to begin with....chicken and the egg conundrum, really.

In July 2007, seriously, reading around, there weren't many professional coders who understood how to optimize for this hardware capability in K10 at the 4S and above stage.

yeah, if there were really good "aware" compilers, that might help but..we'll see. It's good to see AMD actually taking the bull by the horns (as it were) by being proactive with optimizations for compiling (extra SSE5 instructions, etc.)

Thanks again Dave. I hope we could enable and disable these links and their coherency manually, and get a 4S board to use 2x 2300 series and 2x 8300 or something similar. (AFAIK ATM it's hardware controlled through the chip 4 bit license register from the factory though, aswell as the pin connection)

But that would then destroy the +2x higher market pricing on the 4-way+ chips, so mp firms won't do it.

meh...the real news is that the HT3 clock gen is already on the core.

cheers,

dave