From what I understand, what Jacky was getting at with the cache latencies being reduced at a high clockspeed is actually correct. When going to RAM, th eprocessor has to go through all the cache levels of the processor, including the 'slow' L3. The latency of the L3 cache is proportional to a speed (not sure on the terminology) that is increased when the clockspeed is raised. Therefore, with figures quote on the Tech Report site, the cache latecies are 23ns on the slower 2.0Ghz chip and 19ns on the faster (2.5Ghz) chip.
Therefore, increasing the clockspeed
could result in what would seem a higher IPC.
Also, TG Daily slamming AMD with a pro-Intel bias? Well I'll be damned...
Originally Posted by Richie P
From what I understand, what Jacky was getting at with the cache latencies being reduced at a high clockspeed is actually correct. When going to RAM, th eprocessor has to go through all the cache levels of the processor, including the 'slow' L3. The latency of the L3 cache is proportional to a speed (not sure on the terminology) that is increased when the clockspeed is raised. Therefore, with figures quote on the Tech Report site, the cache latecies are 23ns on the slower 2.0Ghz chip and 19ns on the faster (2.5Ghz) chip.
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