K10 Scores starting to surface

[informal]

Yeah that "SPI score" of 31 is a bad fake.Best we ignore that and concentrate on the OCworkbench news.
What could have made them unable to individually clock the separate cores in Phenom ES?Something in the ES chip itself or the bios bug?Very good news about the beta silicon,mobos and bioses hitting >3GHZ OCs with air cooling.This speaks a lot about the potential of the core and at the same time amazes me what AMD managed to do in such a short time from the first reports of clock problems(speedpath issues in the chip).They conquered the whole GHz in a couple of respins(source :dailytech).
Still we can expect 125W spec for first retail 3Ghz version of X4(whenever they are out)

edit:

Latest info from AnandTechStaff:

Throughout the entire prototype and pre-production (as stated in my last message) process, certain features on the CPU, in the BIOS, or on the chipsets have been turned off/on, latencies have changed, etc, etc. This is a normal part of the engineering process as the design is fleshed out and finalized. It does not represent final silicon capabilities and performance.


As I said earlier, I used a poor example as it was not meant to be taken literally spec for spec when comparing engines and CPUs. Regardless of the example, the point was that the platform performance improved significantly as the core speeds improved and this included performance per watt among other indicators. There is a myriad of reasons as to why this occured but considering the early silicon, BIOS, and chipset designs, we could only speculate as to why and I tried to present a few reasons that we honed in on.

If you compare a B00 chip from May to a B02 today, there is a significant difference in performance in all areas (26 seconds in SuperPI 1m for one) and my comments represent observations of what has occurred over this time period. We have final silicon now and results will be posted in the near future. My observations today are different than they were two weeks ago and as the platform matures they will change again.

Once we see the HT 3.0 capable chipsets and Phenom cores mature then we will have an even better indication of the performance of this core design in the consumer market but for now the initial release is Barcelona in the enterprise market.