Barcelona Launch Clock Speeds Changing?

[Donnie27]

Well, I'm just comparing L2 and L3 together. L1 is considerably less latency than L2 or L3, for Intel and AMD. No way should L1 even be near a latency of 10, otherwise, it'd be pointless. Intel currently doesn't use L3 for their consumer products, but they have perfected their L3 to almost L2 standards (if you've seen intel's itanium server products like the montecito, you can't deny that intel hasn't been working on L3), and that is a very large benefit for intel processors as they can load more cache to the processor and distance itself away from the core farther while suffering very little performance loss due to greater latencies. I've noticed AMD has been saying a lot about their L3 cache, but with the latencies that I've seen, it doesn't look to assist in gaining processor performance. These technologies you mention may assist in that, but like I've said, I don't know much about them, so it'd be fruitless (and quite retarded), for me to argue with you on that point (or anyone else for that matter). That does make sense though. I was stating that despite the architecture differences, processors would benefit from lower latency cache. Kind of like processor frequencies. doesn't matter what the architecture is, the higher clocked the processor, the better performance it will output (though the amount it will increase will be discriminatory).

But I think before we continue this discussion, more research would have to be made. If we're going to base most of our information on assumptions, we might as well be a bunch of [h]ardforum noobies having a dumb flamewar.

OK and yes you're right!

[mstp2009]

Yep, throwing huge amount of cache, i.e. transistors, to help with their poor branching/logic is certainly an awesome design.
SOI & large cache are two different things, though there might be a loose correlation. (CPU/architecture is not my best strength)

FYI, branch prediction is better in C2D than K8 (unknown about K10 right now).

http://www.xbitlabs.com/articles/cpu...o-preview.html

[The0men]

If you look back to winnie and vinice cores though (k8) at 2.0ghz the 3200 was as fast (and in most 3d environments even faster) than the equivelent 3.2ghz Intel. So core frequency can be overcome by better archetecture in relationship to efficiency. (smaller clocks usually mean less heat and less power consumption)

[mstp2009]

If you look back to winnie and vinice cores though (k8) at 2.0ghz the 3200 was as fast (and in most 3d environments even faster) than the equivelent 3.2ghz Intel. So core frequency can be overcome by better archetecture in relationship to efficiency. (smaller clocks usually mean less heat and less power consumption)

Yes, I know this. It is the #1 reason C2D is significantly faster than K8. MUCH more efficient architecture (C2D can issue up to 5 INT instructions per cycle, K8 can only do 3).

[lapdog]

Yep, throwing huge amount of cache, i.e. transistors, to help with their poor branching/logic is certainly an awesome design.
SOI & large cache are two different things, though there might be a loose correlation. (CPU/architecture is not my best strength)

Well I guess if the cache works use it...other wise just go the (much slower) hyper transport/IMC (added die size ) for all those misses.

Prescott had so many cache misses it was like a dog chasing it's tail, adding more cache did little to help it. Core2 however with the smaller pipeline and advanced "smart" cache keeps things moving along just fine even with a archaic FSB.

[savantu]

FYI, branch prediction is better in C2D than K8 (unknown about K10 right now).

http://www.xbitlabs.com/articles/cpu...o-preview.html

That's the understatement of the year.

Not only does Core have a significantly better branch prediction unit than K8 , but so does Prescott ( the most advanced till Core came out ) and the whole P4 family.
K8 branch predictor is rudimentary compared with the above.
While K10 will improve it , IMO it will still fall short of Core.

[frankR]

AMD has too much work to do.

They're Quad Core could sink them. Like Intel said, "Native Quad Core at 65 nm, that's suicide".

[Indes]

It was so stupid of them to try this...i believe it was owen wilson in wedding crashers who said..."its the first quarter of the big game and you wanna throw a hail mary?"

[GoThr3k]

Yes, I know this. It is the #1 reason C2D is significantly faster than K8. MUCH more efficient architecture (C2D can issue up to 5 INT instructions per cycle, K8 can only do 3).

wasn't that 4 instead of 5??

[StealthyFish]

AMD has too much work to do.

They're Quad Core could sink them. Like Intel said, "Native Quad Core at 65 nm, that's suicide".

I agree. What is AMD expecting in terms of yields? It's nice to hear about the clock speeds increasing, but at what cost to the consumer...? If yields are bad, prices go up, and consumers pay more. Unless K10 is spectacular, I highly doubt most people will purchase barcelona over kentsfield.

[Donnie27]

Nope. Using MicroOp fusion(when conditional jmp) it can handle up to 5 instructions per clock.

Seen any news on when this will be fixed for Vista Ultimate 64?

[GoThr3k]

Nope. Using MicroOp fusion(when conditional jmp) it can handle up to 5 instructions per clock.

right,damn,need more sleep

[freeloader]

I agree. What is AMD expecting in terms of yields? It's nice to hear about the clock speeds increasing, but at what cost to the consumer...? If yields are bad, prices go up, and consumers pay more. Unless K10 is spectacular, I highly doubt most people will purchase barcelona over kentsfield.

Most people will purchase whatever is cheaper.

[StealthyFish]

Most people will purchase whatever is cheaper.

I've been hearing that a lot of consumers are taking into consideration performance now. Some yahoo or msn article Anyway, the phrases: "native quad core" and "high-yields" just don't sit well with me. Tack on "65 nanometer" and "AMD", and it just looks worse

[Donnie27]

It is not up to the OS, but up to the operating mode. In long(64bit) mode, MicroOp fusion does not work. Thats because the average instruction length is longer then in 32bit mode and the CPU can't fetch 5 instructions. I am not sure how many bytes Penryn can fetch, but Merom can 24bytes, while K10 can 32.

Thanks!

[adamsleath]

http://www.computerpoweruser.com/edi...01%2F20c01.asp
January 2007: nostalgic predictions...