Quote Originally Posted by qgshadow View Post
anyone ???
Here is my 2.
qgshadow please see
For your 1st question see the post by Tony http://www.xtremesystems.org/forums/...d.php?t=114998
Follow the links in post #1, read and test.

400 has an added tweak. I know, I tested 401 and did not have an issue, but it has been too long ago.

I started with

#6 & #49
Originally Posted by remorema
nice work FCG.

for those that dont have a clue for what values to use on those 10-10-10-10 subtimings, heres a tip 3-10-5-13 from top to bottom.
The above values were my starting point.

I am running SPD Enabled because that is my stable value and I get better perfomance. That's 1:1, your running 600Mkz on your ram, my firestix were Elpida chips, they would never do that.

for the sub timing issue, again do some testing for your ram.

Here's my numbers.

using the 3-10-5-13 subtimings above as my starting point
Configure DRAM Timing by SPD [Disabled]
BIOS
4-4-4-12-4-35-3-10-5-13
MemSet
4-4-4-4-12-4-35-2-13-10-3-8-5-4

Code:
---- MBench (C) ver 1.0 (Feb 2002) ----
---- System memory benchmark ----
---- www.x86-secret.com ----

Intel P6 processor (CPUID = 6f6) @ 3500.1MHz
Instruction set support : MMX SSE SSE2 

Access latency			 60.3 ns (211 clocks)

Read datarate (INT)		6919 Mb/s
Write datarate (INT)		2845 Mb/s

Read datarate (MMX)		7582 Mb/s
Write datarate (MMX)		2859 Mb/s

Read datarate (SSE)		7883 Mb/s
Write datarate (SSE)		9035 Mb/s
using Configure DRAM Timing by SPD [Enabled]
BIOS handles it
MemSet
4-4-4-4-12-4-28-2-11-9-2-8-4-4
Code:
---- MBench (C) ver 1.0 (Feb 2002) ----
---- System memory benchmark ----
---- www.x86-secret.com ----

Intel P6 processor (CPUID = 6f6) @ 3500.1MHz
Instruction set support : MMX SSE SSE2 

Access latency			 59.1 ns (207 clocks)

Read datarate (INT)		6952 Mb/s
Write datarate (INT)		2914 Mb/s

Read datarate (MMX)		7630 Mb/s
Write datarate (MMX)		2862 Mb/s

Read datarate (SSE)		7872 Mb/s
Write datarate (SSE)		9086 Mb/s
I think you can spend months tweaking.