Did you ever wonder why everything always ends up in failure?


MSR Fail 0x2a

Processor Hard Power-On Configuration.
(R/W)
Enables and disables processor features; (R)
indicates current processor configuration.

MSR Fail 0x40

Last Branch Record 0 From IP. (R/W)
One of four pairs of last branch record
registers on the last branch record stack. This
part of the stack contains pointers to the
source instruction for one of the last four
branches, exceptions, or interrupts taken by
the processor. See also:
• Last Branch Record Stack TOS at 1C9H
• Section 16.10, “Last Branch, Interrupt, and
Exception Recording (Pentium M
Processors).”

MSR Fail 0x118

Data ECC register D[7:0]: used to write ECC and
read ECC to/from L2

MSR Fail 0x19e

???

MSR Fail 0x400

See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
MACHINE-CHECK ARCHITECTURE

The IA32_MCi_CTL MSR controls error reporting for errors produced by a particular
hardware unit (or group of hardware units). Each of the 64 flags (EEj) represents a
potential error. Setting an EEj flag enables reporting of the associated error and
clearing it disables reporting of the error. The processor does not write changes to
bits that are not implemented.


NOTE

For P6 family processors, processors based on Intel Core microarchi-
tecture (excluding those on which on which CPUID reports
DisplayFamily_DisplayModel as 06H_1AH and onward): the operating
system or executive software must not modify the contents of the
IA32_MC0_CTL MSR. This MSR is internally aliased to the
EBL_CR_POWERON MSR and controls platform-specific error
handling features. System specific firmware (the BIOS) is responsible
for the appropriate initialization of the IA32_MC0_CTL MSR. P6 family
processors only allow the writing of all 1s or all 0s to the
IA32_MCi_CTL MSR.

Now you know why it always ends up in failure.