Quote Originally Posted by saaya View Post
so you think dropping the L1 latency by 25% will result in a 10% performance boost?
Did I say that? No.

I merely suggest you might consider some of the already known changes (L1 latency, for one), in addition to the black box "completely reworked microarchitecture", along with Intel's exec VP stating "significantly improved IPC", before you make claims like: "SB will only improve IPC over Westmere by 2%, on average."

Just because Merom, Nehalem, and probably SB all stick with variants of the P6 *pipeline* doesn't mean there haven't been, and won't continue to be, significant IPC bumps along the way. There's more to the microarchitecture than the basic pipeline.