X48 Rampage Formula Preview.

[mikeyakame]

try setting NB ref to 0.60x, 490mhz fsb needs around 1.55 - 1.57v NB. Also if DRAM clock skews aren't set correctly, it will either lock up, come up with ridiculous amount of errors in memory or fail to post. 333 strap works fine at high FSB if you understand how to tame it. Basically just loosen all memory timings and go from there. 333 strap timings are really tight, PL 9 at 333 seems equivalent to PL 7 at 266 strap. Using PL 8 with 333 strap and 490 fsb, I managed to corrupt some Windows system files! I've gotten memory 100% stable at 490 fsb, but am lost for reasons why heavy CPU activity is locking the system up even with 1.45v Vcore and 1.60v cpu pll, 0.62x cpu gtl+ ref. This is when the mch/cpu skew adjustment feature the P45 boards have would be helpful.

Memory Timings
CAS Latency (CL) 5T
RAS To CAS Delay (tRCD) 5T
RAS Precharge (tRP) 5T
RAS Active Time (tRAS) 18T
Row Refresh Cycle Time (tRFC) 60T
Command Rate (CR) 2T
RAS To RAS Delay (tRRD) 6T
Write Recovery Time (tWR) 14T (Bios WR=7)
Read To Read Delay (tRTR) Same Rank: 5T, Different Rank: 6T
Read To Write Delay (tRTW) 9T
Write To Read Delay (tWTR) Same Rank: 13T, Different Rank: 5T
Write To Write Delay (tWTW) Same Rank: 5T, Different Rank: 6T
Read To Precharge Delay (tRTP) 5T
Write To Precharge Delay (tWTP) 14T
Precharge To Precharge Delay (tPTP) 1T
Refresh Period (tREF) 3120T
DRAM Read ODT 3T
DRAM Write ODT 6T
MCH Read ODT 8T
Performance Level 9
Read Delay Phase Adjust Neutral
DIMM1 Clock Fine Delay 11T
DIMM2 Clock Fine Delay 2T
DIMM3 Clock Fine Delay 10T
DIMM4 Clock Fine Delay 2T

Thats roughly the memory timings that I got to work flawlessly at 490 fsb, using 1:1 divider, 980mhz ddr. Very loose but didnt get around to fine tuning the secondary/tertiary timings as yet, well only a few of them.

With those loose timings, everest cache test was showing ~ 8800MB/s read, ~8700MB/s write, 8100MB/s copy, 57ns latency at 980mhz.