Quote Originally Posted by KTE View Post
Because of cache coherent HT (globally addressable memory address space), 1 Opteron in dual channel has 10,700MB/s peak theoretical bandwidth at DDR2-667 whereas 4 have 42,800MB/s.. correct?
sorry...I misspoke about this.

interprocessor communication (for dual HT link boards) has 1 coherent and 1 additional non-coherent link. so, basically traffic can now be routed two different ways...should offload some of the menial requests..I'm asking for more information on this (as well as testing procedures to accurately show this).

Quote Originally Posted by KTE
From all May 06-July 07 discussions, I recall K10 was to have 4 HT links but that only 3 were to work in 2007 until DCA 2.0 and HT 3.0 is implemented. I specifically recall David Kanter mentioning first launch K10 having 4 HT 1.1 links and one used specifically for I/O in the multi-socket environment which avoids multi-hop snoop traffic. Is this still the case?

So is it supposed to be 3 16-bit ccHT 1.1 links in total for K10?
iirc, it's 2 coherent 16bit links and 1 16-bit HT link. so, 1 coherent p-to-p, 1 p-to-p, and 1 system. 8000s should have 4, iirc.

i'll need to go back and research this a bit more.

cheers,

dave