AMD's Bobcat and Bulldozer

[Manicdan]

Sandy Bridge LGA-2011 will come in 8- and 6-core flavors for the desktop. (in Q3)

There's a table toward the bottom of the wiki entry that may help you keep track of all the variants:

http://en.wikipedia.org/wiki/Sandy_B...oarchitecture)

the only thing that wiki page says is that nothing is known about that, lol

[JF-AMD]

Bulldozer is pretty much an optimized CMT. CMT's supposed to give you twice a core's performance for even greater die-size but AMD settled for greater die-saving but for 80% of a core's performance.. I'm just quoting the slides.

<totally rhetorical question, NOT real numbers>
Which would you rather have:
80% of the performance with 50% of the cost and 50% of the power consumption
100% of the performance with 120% of the cost and 120% of the power consumption
</end rhetorical question>

People keep seeing that 80% number and thinking that it is a compromise. What they don't understand is that by sharing components we are able to add more cores in the same die space and same power budget.

It is by no means 80% of today's performance.

[Florinmocanu]

People do not get one thing.


the comparison of the BD module having 180% performance of 2 cores (which would have 200%) is not done in regards to a 10H core. So... a BD module (with two cores) is not 180% of 2 thuban cores. That is plain dumb to believe.

The 180% is vs 2 proper BD cores. So, instead of having 2 full Bulldozer cores for 200% perf, they chose a module aproach, giving 180% but at 50-60% the size of 2 full cores. Thus, you pack more cores into the same die.

This is exact the thing people like terrace hang on, that BD cores loose 5-10% compared to Thuban. That is just naive to believe. They loose 5-10% in fully threaded applications vs 2 theoretical BD full cores.

[Dimitriman]

Sandy Bridge LGA-2011 will come in 8- and 6-core flavors for the desktop. (in Q3)

There's a table toward the bottom of the wiki entry that may help you keep track of all the variants:

http://en.wikipedia.org/wiki/Sandy_B...oarchitecture)

8 core Sandy has countless times been scheduled as a 2012 product by many reliable sources. Yet you are using wikipedia as your source.

Also, your Q4 2011 for Bulldozer is really crapping on everything that JF and the best AMD sources have been saying. If you want to have honest discussions, its fair. But what you do is simply spread disinformation like a blatant fanboy.

[informal]

Did you stop to think about how Alsup's comments on comp.arch echo AMD's slide bullet point....

Alsup: 5% loss due to u-arch trimming to meet higher frequencies
AMD: "without significant loss in single-thread performance

working components" LoL. Quote the whole thing man,don't leave the crucial parts . This is the module performance "hit" when 2 threads run in parallel.

[end3rkid]

terrace215


sorry, I couldn't resist :P.

[ajaidev]

Something more official would be nice. Everything has been word of mouth lately. 8c without a doubt will come to servers but what about desktops?

Though I think we can trust ajaidev's words but yeah, it'd be nice to have an official word or slides, just to remove all doubts.

This is old "Starting of 2010 old" no other comments....

[Hornet331]

^
lol what was that censoring good for?

[-Sweeper_]

This is old "Starting of 2010 old" no other comments....

wow, 12c/24T ivy-bridge socket compatible with LGA2011 on 2012

co-processor based acceleration? for FP?

[Calmatory]

FPU here we come again.

[blindbox]

This is old "Starting of 2010 old" no other comments....

IMO starting of 2010 counts as new enough for me. (we've been counting on AMD's slides of 2009 and they've been sticking to it at least, except for some parts moving faster than expected)

Let's hope AMD is up to the fight with 6 or 8 modules. Thanks ajaidev

[god_43]

^
lol what was that censoring good for?

to emphasize the future cpu part i would imagine?

[terrace215]

^
lol what was that censoring good for?

I think he's making a joke. It's funny.

[terrace215]

co-processor based acceleration? for FP?

For specialized tasks. Haswell should be very interesting in late '12 / early '13.

[terrace215]

This is exact the thing people like terrace hang on, that BD cores loose 5-10% compared to Thuban. That is just naive to believe.

It's -5% IPC vs Thuban, then higher frequency due to the longer pipeline with faster pipe stages, estimated at 20-25%. This is for a single thread doing integer work.

So says AMD's ex Chief Architect.

IPC is not "performance" it is "performance/frequency". I believe this is the source of much confusion.

BD will have slightly LOWER (integer) IPC for single threads than Phenom-II, which it will attempt to (more than) make up for using speed-racer frequencies. Put together, you could see a performance increase of 15-20% (this depends on GloFo being able to deliver a good enough gate-first 32nm process, which is... uncertain) , but this is nowhere near enough to catch SB, as it just demonstrated a similar gain over Nehalem/Westmere, and Phenom-2 starts in a big hole relative to Nehalem. This is about integer single- (and therefore also low-) threaded workloads.

[terrace215]

sorry, I couldn't resist :P.

Hopefully, the moderators won't be able to resist, either.

[Solus Corvus]

It's -5% IPC vs Thuban, then higher frequency due to the longer pipeline with faster pipe stages, estimated at 20-25%. This is for a single thread doing integer work.

He didn't say vs Thuban, he said vs K10.

Since PII has already surpassed 15-20% versus the original K10, BD has already been passed in performance by Thuban before it's even released. You heard it here first.

[richierich]

why hasn't this clown been banned yet?

[savantu]

He didn't say vs Thuban, he said vs K10.

Since PII has already surpassed 15-20% versus the original K10, BD has already been passed in performance by Thuban before it's even released. You heard it here first.

I wouldn't be surprised for this to hold true core for core at the same frequency.

why hasn't this clown been banned yet?

What will you do when the clown is proven right ? Will you self-ban yourself from here for at least 6 months ?

[Florinmocanu]

It's -5% IPC vs Thuban, then higher frequency due to the longer pipeline with faster pipe stages, estimated at 20-25%. This is for a single thread doing integer work.

No, your wrong.

It's minus 20% performance vs 2 full BD cores. 1 module = 180% of 2 theoretical BD cores. I think that is a clear fact and your just spinning stuff up.

That's the whole point of going for a module. You could have 2 full cores with 200% performance, but with much bigger size. JF-AMD says it as well, they chose smaller die-size so they can pack more modules. Never did they say the 180% is vs Thuban.

Plus, i don't buy the Ex-architect stuff, it's BS. IF you would be a high-end engineer and would, after leaving a company, reveal so much about it, you would get a big law-suit and would probably never get employed by other companies since they would fear you would do the same when working with them.

Usually work contracts have clauses which prevent you from revealing what have you worked during that time and any kind of confidential info.

That's just BS that someone would believe that such a high place engineer would throw smack at AMD. Only a kid would believe professionals act like kids when their career is at stake.

[ajaidev]

No, your wrong.

It's minus 20% performance vs 2 full BD cores. 1 module = 180% of 2 theoretical BD cores. I think that is a clear fact and your just spinning stuff up.

+1

I think you are correct...

[savantu]

No, your wrong.

It's minus 20% performance vs 2 full BD cores. 1 module = 180% of 2 theoretical BD cores. I think that is a clear fact and your just spinning stuff up.

That's the whole point of going for a module. You could have 2 full cores with 200% performance, but with much bigger size. JF-AMD says it as well, they chose smaller die-size so they can pack more modules. Never did they say the 180% is vs Thuban.

You're talking about AMD slides, he's talking about the BD architect comments.
Different things.

Plus, i don't buy the Ex-architect stuff, it's BS. IF you would be a high-end engineer and would, after leaving a company, reveal so much about it, you would get a big law-suit and would probably never get employed by other companies since they would fear you would do the same when working with them.

Usually work contracts have clauses which prevent you from revealing what have you worked during that time and any kind of confidential info.

That's just BS that someone would believe that such a high place engineer would throw smack at AMD. Only a kid would believe professionals act like kids when their career is at stake.

The comment was done on comp.arch.
If you'd bother to loiter around and see who posts there, I wouldn't doubt a single thing of what the guy said. If it were like you said, Andy Glew would be in jail by now. :P

[madcho]

i would think a module it's 160% if it loss 20%, i think it's on 2 cores the loss.

But the advantage is single thread way much faster than tuban, i think. One core ( so one thread ) can run code on the 256bits AVX FP. It's not faster with 2 threads on one module for FP, but the advantage, is less threaded FP code will be faster.

Int should be faster too in ipc even pipe is deeper. As JF- said, PII was 1.5+1.5, BD ( ² ? ) is 2+2. ( ALU+AGU ).

I think it's a good deal. JF- said this week we are going to know what about BD work in 4 threads on 4 modules. Will be auto on 2 modules and 2 modules off or 4 modules on ?

[savantu]

i would think a module it's 160% if it loss 20%, i think it's on 2 cores the loss.

But the advantage is single thread way much faster than tuban, i think. One core ( so one thread ) can run code on the 256bits AVX FP. It's not faster with 2 threads on one module for FP, but the advantage, is less threaded FP code will be faster.

Int should be faster too in ipc even pipe is deeper. As JF- said, PII was 1.5+1.5, BD ( ² ? ) is 2+2. ( ALU+AGU ).

I think it's a good deal. JF- said this week we are going to know what about BD work in 4 threads on 4 modules. Will be auto on 2 modules and 2 modules off or 4 modules on ?

Huh ? K10 has 3 ALUs and 3 AGUs, BD has 2+2. Contrary to what informal&co were hipping around, BD's integer cores are simpler and less powerful than on K10. Which is no surprise, something had to give in order to keep a module size under control.

All the improvements done together with the frequency increase are meant to compensate the 3rd unit. You have the information in the AMD slide ( ...without significant loss on the serial single-threaded workloads components ), you also have the comments of M. Alsup ( ...and
loose a little architectural figure (5%-ish) of merit due to the
microarchitecture ). It all fits together now, irrespective of what marketing is trying to portray.

Without significant loss = loose (5%-ish )

AMD is giving up single threaded performance and is focusing on through-output. They've realize it is pointless to try and compete with Intel on "fat" cores ( already in commercial benchmarks they need a 2-to-1 ratio to stay competitive with Xeons ) so the alternative path they are taking is to cram as many cores as possible in a given die size and clock those simple cores as high as possible.

Magny Cours isn't adequate for this since the core size is still too big and the core advantage over Xeons at the same process node is too small. With MC, AMD had a 50% advantage in the number of cores. With BD they will have 60% ( and much higher frequency ) over same timeframe Xeon and this will only increase in the future.

[Sunfire]

Huh ? K10 has 3 ALUs and 3 AGUs, BD has 2+2. *snipping blah-blah-blah*

Please read this thread from the beginning, and you will find the answer. No need to speculate.

Thank you!