MMM
Page 2 of 2 FirstFirst 12
Results 26 to 39 of 39

Thread: AMD to ditch 1mbx2 cache am2 processors

  1. #26
    Xtreme Addict
    Join Date
    Mar 2006
    Location
    Sillicon Valley, California
    Posts
    1,261
    Quote Originally Posted by AJF
    I guess it makes sense, but they'll probably increase it again once K8L drops, maybe a shift to the use of ZRAM. Short-term, they're aiming for a shift to 65nm and increased clock speeds, or so it seems.

    ZRAM is a technology hyped created by those without any technical backgrounds (i.e. overclockers, AMD fan, etc).

    If you actually read the technical white papers and publications, ZRAM, although consumes little real estate, is way too slow to be used as L1 or L2 cache. It's feasible to use it as L3 cache, but the actual die savings is minimal if you look at the recently published K8L spec.

    BTW, if you look at the most recent published die picture of K8L, AMD did not replace any cache with ZRAM yet.

  2. #27
    Xtreme Enthusiast
    Join Date
    Aug 2004
    Location
    Scotland
    Posts
    609
    Quote Originally Posted by taemun
    They haven't even landed in this country yet and they are already axed.....
    yeah, I've been watching for 4000+ in the UK ...
    abit IP35 Pro, E6600, HD3870, FSP FX700-GLN
    abit AB9 QuadGT, E6400, 7900GTO, FSP FX600-GLN
    abit AX78 x2
    Asus P5N-E SLI, E6600, 8800GTS, Tagan 530W

  3. #28
    Registered User
    Join Date
    Oct 2002
    Location
    durban , south africa
    Posts
    11
    i realy think it makes sense of amd to make all those 1mb per core cache chips into opterons - you have the standard desktop series all have 512mb cache per core - and rename all the 1mb cache per core chips to the workstation opteron family without having to make any changes at the production lines

    wonder if thats whats really happening here

  4. #29
    Xtreme Member
    Join Date
    Mar 2006
    Posts
    136
    Quote Originally Posted by Pipi
    AMD isn't affected by the size of cache that much because of the on-die memory controller. That's how it was on s939 though. DDR2 has looser timings which hurt AMD's performance. Intel's CPUs on the other hand LOVE bigger cache.
    Quote Originally Posted by vitaminc
    Can't be more wrong than this.

    Regardless of architecture, more cache is always better. Simple fact: Opterons have larger cache than the Athlon 64s.
    It can certainly be more wrong, although what Pipi said about DDR2 having looser timings is false.

    The big L1, the IMC and the write policy (which reduces the length of the R/W queues relative to P4s) make the L2 size less significant for AMD CPUs. The P4s additional cache-to-RAM update-rate stresses the importance of aggressive cache prefetching (thus the cache size) because of the increased loaded latency of the memory subsystem. And there is no general rule stating that more cache is always better, although it is the case with the K8 family because any L2 size has similar latencies.

  5. #30
    Xtreme Member
    Join Date
    Nov 2005
    Posts
    100
    Quote Originally Posted by vitaminc
    ZRAM is a technology hyped created by those without any technical backgrounds (i.e. overclockers, AMD fan, etc).

    If you actually read the technical white papers and publications, ZRAM, although consumes little real estate, is way too slow to be used as L1 or L2 cache. It's feasible to use it as L3 cache, but the actual die savings is minimal if you look at the recently published K8L spec.

    BTW, if you look at the most recent published die picture of K8L, AMD did not replace any cache with ZRAM yet.

    My bad, I didn't mean to say that ZRAM would be a replacement for L2, because it is, as you said, much too slow. Also as you pointed out, it would be quite applicable for L3, which will probably be introduced in an AMD product "shortly" after K8L.

    I have no illusions of ZRAM being tossed into a L2 cache position until the latencies involved drop dramatically. It is, however, great stuff that very well may prove to be a great enhancement in future products. Probably when quad-core chips start rolling out. Not sure what you even meant by your last sentence.

    AMD has done other things for improvements in K8L...but that's old news.

  6. #31
    Xtreme Member
    Join Date
    Dec 2005
    Location
    Toronto, Canada
    Posts
    120
    Quote Originally Posted by _damien_
    It can certainly be more wrong, although what Pipi said about DDR2 having looser timings is false.

    The big L1, the IMC and the write policy (which reduces the length of the R/W queues relative to P4s) make the L2 size less significant for AMD CPUs. The P4s additional cache-to-RAM update-rate stresses the importance of aggressive cache prefetching (thus the cache size) because of the increased loaded latency of the memory subsystem. And there is no general rule stating that more cache is always better, although it is the case with the K8 family because any L2 size has similar latencies.
    I would say more cache is always better, but only if you hold all other factors constant.

    Prescott to Prescott-2M didn't produce much gains on cache as the cahce used on Prescott-2M is slower then the original Prescott.

  7. #32
    Xtreme Addict
    Join Date
    Jan 2005
    Posts
    1,730
    Quote Originally Posted by _damien_
    It can certainly be more wrong, although what Pipi said about DDR2 having looser timings is false.

    The big L1, the IMC and the write policy (which reduces the length of the R/W queues relative to P4s) make the L2 size less significant for AMD CPUs. The P4s additional cache-to-RAM update-rate stresses the importance of aggressive cache prefetching (thus the cache size) because of the increased loaded latency of the memory subsystem. [b] And there is no general rule stating that more cache is always better, [b] although it is the case with the K8 family because any L2 size has similar latencies.
    Pat Gelsinger said " cache+exceptional prefetch vs. IMC , cache always wins " Look at Conroe...

    And to quote him again " Who cares if the RAM latency is 70ns or 100 ? I can serve it in 4ns from the cache " talking about the difference between IMC and MC in the NB.

  8. #33
    Xtreme Member
    Join Date
    Jun 2006
    Location
    smyrna, TN
    Posts
    379
    I can't believe they're doing this unless they're just trying to boost fx sales, but it doesn't make sense to me

  9. #34
    Xtreme Member
    Join Date
    Mar 2006
    Posts
    136
    Quote Originally Posted by savantu
    Pat Gelsinger said " cache+exceptional prefetch vs. IMC , cache always wins " Look at Conroe...
    Well, I never denied that. I was merely explaining why the cache size is of less importance to AMD CPUs than P4s. The IMC is certainly part of the explanation, because it reduces the cache miss penalty. Sticking with the same architecture, and comparing two CPUs whose only difference is the L2 size, there would be less performance difference between the two AMD CPUs than the Intel CPUs. So reducing the L2 size takes a smaller performance hit for AMDs.

    Quote Originally Posted by savantu
    And to quote him again " Who cares if the RAM latency is 70ns or 100 ? I can serve it in 4ns from the cache " talking about the difference between IMC and MC in the NB.
    See above

  10. #35
    Xtreme Member
    Join Date
    Mar 2006
    Posts
    136
    Quote Originally Posted by coldpower27
    I would say more cache is always better, but only if you hold all other factors constant.
    ...which is another way of saying more isn't always better...

  11. #36
    Xtreme Addict
    Join Date
    Mar 2006
    Location
    Sillicon Valley, California
    Posts
    1,261
    Quote Originally Posted by toddm27
    I can't believe they're doing this unless they're just trying to boost fx sales, but it doesn't make sense to me
    capacity, capacity, capacity.

    AMD is bone dry and can't grind out more juices as their new fab is ramping while old fab is transitioning to 65nm/300mm.

    too much sex could kill.

  12. #37
    Xtreme Member
    Join Date
    Apr 2005
    Posts
    373
    To keep things straight, the new 1207 socket will be the Opteron socket for DDR2 correct? The only processors for the new AM2 940 are Sempy's A64's FX's and X2's???
    Core 2 Duo E8400 @ 4ghz
    2GB PC2-6400 @ 445/890 4, 4, 4, 12
    ATI HD4850 @ stock
    Gigabyte P35-DS3L
    El Cheapo 500w PSU with dual 12v rails
    16X DVD+/- R/W

  13. #38
    Registered User
    Join Date
    Jun 2005
    Posts
    81
    Have me FedX tracking # on a
    AMD Athlon 64 X2 4000+ 2.0GHz, Winsdor, Dual-Core, 2x1MB

    http://www.excaliberpc.com/AMD_Athlo...id-565923.html

    the guy talked like they had alot more than 5 - ordered last night

  14. #39
    Xtreme Addict
    Join Date
    Mar 2006
    Location
    Sillicon Valley, California
    Posts
    1,261
    Quote Originally Posted by Rickster_64
    To keep things straight, the new 1207 socket will be the Opteron socket for DDR2 correct? The only processors for the new AM2 940 are Sempy's A64's FX's and X2's???
    Correct.

    New Opterons will only work in Socket F. There will be no Socket AM2 Opterons available.

    Smart move by AMD to prevent its own market erosions by overlapping processors, aka overclockers getting opty on desktop or ODM putting athlon on server.

Page 2 of 2 FirstFirst 12

Bookmarks

Bookmarks

Posting Permissions

  • You may not post new threads
  • You may not post replies
  • You may not post attachments
  • You may not edit your posts
  •