AMD to ditch 1mbx2 cache am2 processors

[vitaminc]

I guess it makes sense, but they'll probably increase it again once K8L drops, maybe a shift to the use of ZRAM. Short-term, they're aiming for a shift to 65nm and increased clock speeds, or so it seems.

ZRAM is a technology hyped created by those without any technical backgrounds (i.e. overclockers, AMD fan, etc).

If you actually read the technical white papers and publications, ZRAM, although consumes little real estate, is way too slow to be used as L1 or L2 cache. It's feasible to use it as L3 cache, but the actual die savings is minimal if you look at the recently published K8L spec.

BTW, if you look at the most recent published die picture of K8L, AMD did not replace any cache with ZRAM yet.

[Heidfirst]

They haven't even landed in this country yet and they are already axed.....

yeah, I've been watching for 4000+ in the UK ...

[naughty]

i realy think it makes sense of amd to make all those 1mb per core cache chips into opterons - you have the standard desktop series all have 512mb cache per core - and rename all the 1mb cache per core chips to the workstation opteron family without having to make any changes at the production lines

wonder if thats whats really happening here

[_damien_]

AMD isn't affected by the size of cache that much because of the on-die memory controller. That's how it was on s939 though. DDR2 has looser timings which hurt AMD's performance. Intel's CPUs on the other hand LOVE bigger cache.

Can't be more wrong than this.

Regardless of architecture, more cache is always better. Simple fact: Opterons have larger cache than the Athlon 64s.

It can certainly be more wrong, although what Pipi said about DDR2 having looser timings is false.

The big L1, the IMC and the write policy (which reduces the length of the R/W queues relative to P4s) make the L2 size less significant for AMD CPUs. The P4s additional cache-to-RAM update-rate stresses the importance of aggressive cache prefetching (thus the cache size) because of the increased loaded latency of the memory subsystem. And there is no general rule stating that more cache is always better, although it is the case with the K8 family because any L2 size has similar latencies.

[AJF]

ZRAM is a technology hyped created by those without any technical backgrounds (i.e. overclockers, AMD fan, etc).

If you actually read the technical white papers and publications, ZRAM, although consumes little real estate, is way too slow to be used as L1 or L2 cache. It's feasible to use it as L3 cache, but the actual die savings is minimal if you look at the recently published K8L spec.

BTW, if you look at the most recent published die picture of K8L, AMD did not replace any cache with ZRAM yet.

My bad, I didn't mean to say that ZRAM would be a replacement for L2, because it is, as you said, much too slow. Also as you pointed out, it would be quite applicable for L3, which will probably be introduced in an AMD product "shortly" after K8L.

I have no illusions of ZRAM being tossed into a L2 cache position until the latencies involved drop dramatically. It is, however, great stuff that very well may prove to be a great enhancement in future products. Probably when quad-core chips start rolling out. Not sure what you even meant by your last sentence.

AMD has done other things for improvements in K8L...but that's old news.

[coldpower27]

It can certainly be more wrong, although what Pipi said about DDR2 having looser timings is false.

The big L1, the IMC and the write policy (which reduces the length of the R/W queues relative to P4s) make the L2 size less significant for AMD CPUs. The P4s additional cache-to-RAM update-rate stresses the importance of aggressive cache prefetching (thus the cache size) because of the increased loaded latency of the memory subsystem. And there is no general rule stating that more cache is always better, although it is the case with the K8 family because any L2 size has similar latencies.

I would say more cache is always better, but only if you hold all other factors constant.

Prescott to Prescott-2M didn't produce much gains on cache as the cahce used on Prescott-2M is slower then the original Prescott.

[savantu]

It can certainly be more wrong, although what Pipi said about DDR2 having looser timings is false.

The big L1, the IMC and the write policy (which reduces the length of the R/W queues relative to P4s) make the L2 size less significant for AMD CPUs. The P4s additional cache-to-RAM update-rate stresses the importance of aggressive cache prefetching (thus the cache size) because of the increased loaded latency of the memory subsystem. [b] And there is no general rule stating that more cache is always better, [b] although it is the case with the K8 family because any L2 size has similar latencies.

Pat Gelsinger said " cache+exceptional prefetch vs. IMC , cache always wins " Look at Conroe...

And to quote him again " Who cares if the RAM latency is 70ns or 100 ? I can serve it in 4ns from the cache " talking about the difference between IMC and MC in the NB.

[toddm27]

I can't believe they're doing this unless they're just trying to boost fx sales, but it doesn't make sense to me

[_damien_]

Pat Gelsinger said " cache+exceptional prefetch vs. IMC , cache always wins " Look at Conroe...

Well, I never denied that. I was merely explaining why the cache size is of less importance to AMD CPUs than P4s. The IMC is certainly part of the explanation, because it reduces the cache miss penalty. Sticking with the same architecture, and comparing two CPUs whose only difference is the L2 size, there would be less performance difference between the two AMD CPUs than the Intel CPUs. So reducing the L2 size takes a smaller performance hit for AMDs.

And to quote him again " Who cares if the RAM latency is 70ns or 100 ? I can serve it in 4ns from the cache " talking about the difference between IMC and MC in the NB.

See above

[_damien_]

I would say more cache is always better, but only if you hold all other factors constant.

...which is another way of saying more isn't always better...

[vitaminc]

I can't believe they're doing this unless they're just trying to boost fx sales, but it doesn't make sense to me

capacity, capacity, capacity.

AMD is bone dry and can't grind out more juices as their new fab is ramping while old fab is transitioning to 65nm/300mm.

too much sex could kill.

[Rickster_64]

To keep things straight, the new 1207 socket will be the Opteron socket for DDR2 correct? The only processors for the new AM2 940 are Sempy's A64's FX's and X2's???

[Amiteriver]

Have me FedX tracking # on a
AMD Athlon 64 X2 4000+ 2.0GHz, Winsdor, Dual-Core, 2x1MB

http://www.excaliberpc.com/AMD_Athlo...id-565923.html

the guy talked like they had alot more than 5 - ordered last night

[vitaminc]

To keep things straight, the new 1207 socket will be the Opteron socket for DDR2 correct? The only processors for the new AM2 940 are Sempy's A64's FX's and X2's???

Correct.

New Opterons will only work in Socket F. There will be no Socket AM2 Opterons available.

Smart move by AMD to prevent its own market erosions by overlapping processors, aka overclockers getting opty on desktop or ODM putting athlon on server.