**Official DFI LanParty UT 790FX-M2R Review/Overclock/Guide Thread**

[justapost]

What do you mean by weak and normal mode here?

Hmm.. it modifies them on all Phenoms according to guide AFAIK. What voltage and VID did it give you?
Try 0x3000100A from 1.25VID, it should give you a ~10W AC idling increase in power. If not then something with your CPU MSR is going iffy.

Voltage (in CPU-Z and Everest) did not change, AMD Power Monitor showed what I wrote into the register. The board seems to simply not use VID's. Every board seems to have it's own implementation. Must read the clock-chip's specs.

Yeah I saw it, it's very weird and well, too high

Gonna look into that tonight, happens on various power consumption's in idle so i can sort out psu efficiency jumps.

Thanks but are you sure that's their only relevance?

K, I wrote down all the registers related to P-States and power. I'll post a list here soon with all the variables.

Have you actually tried these work? Very good options if they do.

Well the resolution of the super-io chips reading seems to have a lower resolution ~0.016V, so that can not be used for verification. But I had situations where an +0.00625V helped to get the system stable.

What (&#37 Vdrop and Vdroop does the board have?

I'll give ya a few examples:

cpu frequency/bios/idle/load
200x11,5/1,1625/1,152/1,152
200x12/1,175/1,168/1,168
200x13/1,35/1,328/1,344
219x12/1,38125/1,376/1,376

200x13 might work with a lower voltage all others use the minimal possible voltage (~8hrs prime95+3dmark+internet+some cad work).
From bios to load it's in the rounding area. idle might sometimes be 0.016V lower.

[KTE]

Don't have those options at all, DFI BIOS has allowed so much options. DS are all 1.00x but DRAM Drivers show up as "Weak mode = Disabled" in AOD.

Voltage (in CPU-Z and Everest) did not change, AMD Power Monitor showed what I wrote into the register. The board seems to simply not use VID's. Every board seems to have it's own implementation. Must read the clock-chip's specs.

Must be, VIDs in BIOS are used to provide higher/lower voltages. With VIDs you can access very low volt increases (if you check them all, they're lower than +/-0.005V). But some BIOSes have the option to override VID settings, so no matter what VID you have it gives you all the VID higher and lower voltage options combined. Yours seems to be one of them, DFI definitely does. Saves a lot of work.

cpu frequency/bios/idle/load
200x11,5/1,1625/1,152/1,152
200x12/1,175/1,168/1,168
200x13/1,35/1,328/1,344
219x12/1,38125/1,376/1,376

Nice, no vdroop which is excellent for stability testing/oc stability but bad for power consumption and CPU/MB wear out but you have some vdrop I'm not too fond of. The MSI has high vdroop but lower vdrop than that.

[justapost]

P-State Current Limit Register

0xc0010061: 0x00000000 0x00000010

[6:4] PStatMaxVal (lowest p-state, highest value) 1
[2:0] CurPstateLimit (lowest temp related p-state, highest value, max from htc and stc p-states) 0

P-State Control Register

0xc0010062: 0x00000000 0x00000000

[2:0] PstateCmd (last written p-state) 0

P-State Status Register

0xc0010063: 0x00000000 0x00000000

[2:0] CurPstate (active p-state) 0

P-State 0

0xc0010064: 0x800001BC 0x3000300A

[63] PstateEn: 1 (register is valid after reset)
[41:40] IddDiv: 1 (10A)
[39:32] IddValue: 94
[31:25] NbVid: 0011000b 1,25V
[22] NbDid: 0 (1)
[15:9] CpuVid: 0011000b 1,25V
[8:6] CpuDid: 0 (1)
[5:0] CpuFid: 10

CPU COF = 2600MHz

P-State 1

0xc0010065: 0x80000187 0x30005047

[63] PstateEn: 1 (register is valid after reset)
[41:40] IddDiv: 1 (10A)
[39:32] IddValue: 135
[31:25] NbVid: 0011000b 1,25V
[22] NbDid: 0 (1)
[15:9] CpuVid: 0101000b 1,05V
[8:6] CpuDid: 1 (2)
[5:0] CpuFid: 7

CPU COF = 1150MHz

P-State 2

0xc0010066: 0x00000000 0x30000000

[63] PstateEn: 0 (register is invalid after reset)

P-State 3

0xc0010067: 0x00000000 0x30000000

[63] PstateEn: 0 (register is invalid after reset)

P-State 4

0xc0010068: 0x00000000 0x30000000

[63] PstateEn: 0 (register is invalid after reset)

COFVID Control Register

0xc0010070: 0x00000000 0x3000300A

[31:25] NbVid: 0011000b 1,25V
[22] NbDid: 0 (1)
[18:16] PstateId: 0
[15:9] CpuVid: 0011000b 1,25V
[8:6] CpuDid: 0 (1)
[5:0] CpuFid: 10

COFVID Status Register

0xc0010071: 0x00800001 0x3000300A

[63:59] MaxNbFid:
[58:56] CurPstateLimit: 0
[54:49] MaxCpuCof: 0 (no frequency limit)
[48:42] MinVid: 0 (no minimum specified)
[41:35] MaxVid: 0 (no maximum specified)
[34:32] StartupPstate: 1
[31:25] CurNbVid: 0011000b 1,25V
[22] CurNbDid: 0 (1)
[18:16] CurPstate: 0
[15:9] CurCpuVid: 0011000b 1,25V
[8:6] CurCpuDid: 0 (1)
[5:0] CurCpuFid: 10

Hardware Thermal Control (HTC) Register

F3x64: 0x127F0004

[30:28] HtcPstateLimit: 1 (p-state limit in htc mode)
[27:24] HtcHystLmt: 2
[23] HtcSlewSel: 0
[22:16] HtcTmpLmt: 127 (115,5 Tctl)
[7] PslApicLoEn: 0 (no interrupt used for low end change)
[6] PslApicHiEn: 0 (no interrupt used for high end change)
[4] HtcAct: 0 (Prozessor not in HTC state)
[0] HtcEn: 0 (Prozessor not capable of entering the HTC-active state)

Software Thermal Control (STC) Register

F3x68: 0x10000000

[30:28] StcPstateLimit: 1 (p-state limit in htc mode)

Power Control Miscellaneous Register

F3xA0: 0xA00A2800

[31] CofVidProg: 1 (VID and PID of the p-state had been applied to the prozessor)
[29] SlamVidMode: 1 (Voltage is slamed not stepped)
[27:16] PStateId: 0
[13:11] PllLockTime: 1010b (PLL need 16 microseconds to apply a new FID on a p-state change)
[8] PviMode: 0 (Serial VID interface selected)
[7] PsiVidEn: 0 (PSI_L is always high)
[6:0] PsiVid: 0 (unused cuz PsiVidEn is zero)

Reported Temperature Control Register

F3xA4: 0x1A1C9880

[31:21] CurTmp: 208 (26 ° * Tctl)
Note: (see BKDG 2.10.1)

Tctl is a non-physical temperature on an arbitrary scale measured in degrees.... It specifies the prozessor temperature relative to the point at which the system must supply the maximum cooling for the prozessor's specified maximum case temperature and maximum thermal power dissipation.

[17:16] CurTmpSel: 0 (CurTmp provides the read-only Tctl value)
[12:8] PerStepTimeDn: 18h (1 millisecond)
[7] TmpSlewDnEn: 1 (Slew the rate controls in the downward direction are enabled)
[6:5] TmpMaxDiffUp: 0 (Upward slewing disabled)
[4:0] PerStepTimeUp: 0 (raniging from 1 to 8 milliseconds)

If vid's are used i guess it's the voltage step mode.

[justapost]

Funny stuff:

MSR-Editor:
0xc0010064: 0x800001BC 0x3000300A (p-state 0)
0xc0010065: 0x80000187 0x30005040 (p-state 1)

Bios:
CnQ: Enabled:
CPU freq: Auto
CPU voltage: Auto

WinXP:
Power Saving mode

Now I have CnQ with 800MHz vs. 2600MHz.

Note: With CnQ enabled before MSR Editor modification the p-states have to switch once, then the modified values get used. Also the VID's are applied and CPU-Z shows the vcore also changes, but that can be the auto setting also. Will try NB speed modification with p-states now.

[KTE]

Thanks Achim.

I have some qs for you;

0xc0010071: 0x00800001 0x3000300A

MaxNbFid:
CurPstateLimit: 0
MaxCpuCof: 0 (no frequency limit)
MinVid: 0 (no minimum specified)
MaxVid: 0 (no maximum specified)
StartupPstate: 1
CurNbVid: 0011000b 1,25V
CurNbDid: 0 (1)
CurPstate: 0
CurCpuVid: 0011000b 1,25V
CurCpuDid: 0 (1)
CurCpuFid: 10

Where were you getting the NB VID and CPU FID from there?
The NB VID doesn't seem to the as the guide states in that register but that only seems to show the CPU VID in that MSR for me (?).

Have you tested changing DID with this MB?

Reported Temperature Control Register

F3xA4: 0x1A1C9880

CurTmp: 208 (26°C)
CurTmpSel: 0 (CurTmp provides the read-only Tctl value)
PerStepTimeDn: 18h (1 millisecond)
TmpSlewDnEn: 1 (Slew the rate controls in the downward direction are enabled)
TmpMaxDiffUp: 0 (Upward slewing disabled)
PerStepTimeUp: 0 (raniging from 1 to 8 milliseconds)

How did you access that address?
Also, if Tcontrol is reading 0 then that means the 26C CurrentT is real according to the probes (which is faulty).

Maybe this Tctl value can be changed to give more accrate temps.

[justapost]

So it is possible to define at least two p-states with individual CPU VID/DID, CPU FID and NB DID.
There are two other variables in the p-state registers IddValue and IddDiv. Those are used during system start in the prozessor-systemboard power delivery compatibility check (see. BKDG 2.4.2.7) to calculate the amps the processor needs in the p-state. The guide also mentions that for each p-state an acpi prozessor p-state object should be created. I assume those will use the amp value to decide when to switch to another p-state. If thats correct it could be used to detect the currently used amps by tweaking p-state 1 till the system switches to state 1 under load.
The first bit in each p-states register defines if the state is valid, so it might be possible to define more than two states.

[justapost]

Where were you getting the NB VID and CPU FID from there?
The NB VID doesn't seem to the as the guide states in that register but that only seems to show the CPU VID in that MSR for me (?).

CPU VID and NN VID are at 1.25V if i do not define em different in the p-state registers and apply em using cnq mode as described above.
CPU FID are bits 0:5 (0Ah=10). Realized i better had added the bits to the previous post after i nearly finished. Hmm i'm lazy but i'm gonna edit.

Have you tested changing DID with this MB?

A NB divider of two boots (9/2 with 800MHz HT) and shows up in the MSR register (..71) but not in cpu-z. Tried to change it on the fly with the msr editor and the system froze.

How did you access that address?

That is on the same page as the nb multi in wpcredit (Device 24:Function 3) is F3xXX(X with baredit).

Also, if Tcontrol is reading 0 then that means the 26C CurrentT is real according to the probes (which is faulty).
Maybe this Tctl value can be changed to give more accrate temps.

Only skimmed over the docs don't have a good oversight over temperature handling atm.

EDIT: Updated previous post added bits used for the variables and an info abou tclt (it's an delta and no absolute temperature)

[KTE]

Yeah that CnQ P-State 1 works realtime. I've messed about with it earlier - old value is RDMSR, new value is WRMSR (stable):



4x is lowest multi limit, freeze below that.
I'll edit post with a full reply in a while, bit busy yet.

EDIT (updated above pic):
That above is lowest voltage for NB/CPU stable too, any lower it freezes.

I'm running near enough exact settings as you Achim, especially CPU settings. My system idles 108W AC @ this:



And with CnQ enabled now in the first pic above, it idles 94W AC (2x HDs, 2x 5V fans). Very good options to access and edit these registers IMHO, don't you think?

Here are my settings I run with those two:

Current: MSR 0xC0010070
0x00000000 0x4800340A (1.100V NB/1.225V CPU)

P0: MSR 0xC0010064
0x800001BC 0x4800340A (1.100V NB/1.225V CPU)

P1: MSR 0xC0010065
0x80000187 0x48007040 (800/1800 0.850V/1.100V)

V above = VID.

As you can see, VIDs is how the processor controls all volts internally even for CPU and NB in all P-States including boot states. So that 1.250VID NB is 1.232V/1.240V. But NB VID never changed in P-State 1 unless you do this manually. I know NB FID cannot be changed after boot and that's why it won't change where HTC is active where GCLK downclocks nor when you have CnQ enabled but ... messing with the NB VID register it works fully, like so:

NB VID Control
30h 0011000b 1.250V
....
38h 1.200V
39h  1.200V
40h 1.150V
41h 1.150V
42h 1.138V
43h 1.138V
44h 1.125V
45h 1.125V
46h 1.112V
47h 1.112V
48h 1.100V
49h 1.100V
50h 1.050V

Those are only ones I can access yet because I don't have my saved ss/txt files here.

I can change CPU DID to 1 and 2 real-time but anything higher is no go.
I've not tried NB DID yet.

Yep, power is controlled by the CPU VID, NB VID, IddValue and IddDiv which also sets the TDP and that changes the Tcontrol and Tcontrol max limits apparently.
BTW I know Tcontrol is not the actual temp value in degrees but just an arbitrary value to represent it. That's why it's allowed to read subzero at high ambients.
What happened was, my first 9500 which is the main one I experimented highly with temps, it read the temp in BIOS the same as the physical Tcase temp most likely because it was missing the offset, but the ones after that were all different. This 9600BE reads the register properly (sub-ambients).

Same with F3xA4, I asked about it because on the NB register access it read 0b for me so I thought there's another way. It reads correctly now but many times it blanks out or reads F's.

Thanks for adding the bits, makes me not have to read the guide. Although you did make me read up the guide once again you know...

[justapost]

Sorted out the usb power consumption issue. Removed one of the 4pin 12V connectors now the stick consumes ~5W AC.

Saw you messed with p-states must have missed that you looked into CnQ,sry. I'm pretty happy that it works that way. With 800MHz and ~0.9V the system requires ~110W AC idle, untweaked CnQ in idle 120W, 2600GHz ~1,28V in idle ~150W. (with one pwm fan and only one sata hd, everything else as in sig). So I save ~10W against CnQ and ~40W against normal oced 2.6GHz mode.

It's also a nice way to test higher multi/voltage combinations. Use a save setting for state 1 and the test setting in state 0, as soon as you stop load you are save.

Would be a great feature if the bios allows defining both p-states settings.

[justapost]

A = NB VID ,B = CPU VID

78h: 0.80V
70h: 0.85V
68h: 0.90V
60h: 0.95V
58h: 1.00V
50h: 1.15V
48h: 1.10V
40h: 1.15V
38h: 1.20V
30h: 1.25V
28h: 1.30V
20h: 1.35V
18h: 1.40V
10h: 1.45V
08h: 1.50V
00h: 1.55V

C = CPU FID/CPU DID

Divisors of 2 only work if the frequency can not be described with a 1 divisor.

40h: 800 MHz
41h: 850 MHz
42h: 900 MHz
43h: 950 MHz
44h: 1000 MHz
45h: 1050 MHz
46h: 1100 MHz
47h: 1150 MHz
48h: 1200 MHz
49h: 1250 MHz
4Ah: 1300 MHz
4Bh: 1350 MHz
4Ch: 1400 MHz
4Dh: 1450 MHz
4Eh: 1500 MHz
4Fh: 1550 MHz
00h: 1600 MHz
51h: 1650 MHz
01h: 1700 MHz
53h: 1750 MHz
02h: 1800 MHz
55h: 1850 MHz
03h: 1900 MHz
57h: 1950 MHz
04h: 2000 MHz
59h: 2050 MHz
05h: 2100 MHz
5Bh: 2150 MHz
06h: 2200 MHz
5Dh: 2250 MHz
07h: 2300 MHz
5Fh: 2350 MHz
08h: 2400 MHz
61h: 2450 MHz
09h: 2500 MHz
63h: 2550 MHz
0Ah: 2600 MHz
65h: 2650 MHz
0Bh: 2700 MHz
67h: 2750 MHz
0Ch: 2800 MHz
69h: 2850 MHz
0Dh: 2900 MHz
6Bh: 2950 MHz
0Eh: 3000 MHz

Pattern:

AAxxxxxx NBVID
xxxxBBxx CPUVID
xxxxxxCC CPUFID/DID

A*2^24+B*2^8+C

I do not modify the bits [63:32] for the p-states. With above tables and the pattern i hope it's obvious how to define your own p-states.

Example:

p-state 0:

2.6GHZ 1.275V/1.1V

NBVID 1.1V 48h
CPUVID 1.275V 2Ch
CPUFID 2.6GHz 0Ah

MSRC001_00[64] Bits [31:0] 48002C0Ah

p-state 1:

0.8GHZ 0.85V/1.1V

NBVID 1.1V 48h
CPUVID 0.85V 70h
CPUFID 0.8GHz 40h

MSRC001_00[65] Bits [31:0] 48007040h

To apply it with RW-Everything use that script:

>cpu 1
>wrmsr 0xc0010064 0x800001BC 0x48002C0A
>wrmsr 0xc0010065 0x80000187 0x48007040
>cpu 2
>wrmsr 0xc0010064 0x800001BC 0x48002C0A
>wrmsr 0xc0010065 0x80000187 0x48007040
>cpu 3
>wrmsr 0xc0010064 0x800001BC 0x48002C0A
>wrmsr 0xc0010065 0x80000187 0x48007040
>cpu 4
>wrmsr 0xc0010064 0x800001BC 0x48002C0A
>wrmsr 0xc0010065 0x80000187 0x48007040
>rwexit

Note: The ">" must be in the text file.

Another Note: BKDG mentions that a NB DID must be the same in all p-states, as changing the NB FID requires an reboot NB frequency can not be modified via p-states.

[KTE]

Yep, just checked out the guide, quote BKDG:

The processor supports dynamic P-state changes in up to 5 independently-controllable frequency planes: each
CPU core (up to 4) and the NB; and up to 2 independently-controllable voltage planes: VDD, and VDDNB.

MSRC001_0062 holds the P-State transition for each core so you can first define a separate P-State under MSRC001_00[68:64] and then using MSRC001_0062 set a separate P-State from 0-4 for each core individually. So P0 is maximum power state, P1 for core 0, P2 for core 1, P3 for core 2 and P4 for core 3. Quite nifty don't you think?

RWE doesn't work for me, it just gets stuck and deletes the file data.

[justapost]

Yep, just checked out the guide, quote BKDG:

MSRC001_0062 holds the P-State transition for each core so you can first define a separate P-State under MSRC001_00[68:64] and then using MSRC001_0062 set a separate P-State from 0-4 for each core individually. So P0 is maximum power state, P1 for core 0, P2 for core 1, P3 for core 2 and P4 for core 3. Quite nifty don't you think?

RWE doesn't work for me, it just gets stuck and deletes the file data.

Each core has five p-states. At least two of em work have not tried more. So
you can use it to define individual multis and volts for each core. In terms of the volts the max under all cores in a defined p-state is used. The multis realy apply individual.
Tried the CPU FID's with a two divisor. Not all of em work. Above 5Bh the system freezes.
What happens if you enter the commands (without the ">" character) in rwedit manual?

[KTE]

^Not tried it manually but the same thing happens if I remove the ">" prefix from the file.
I'll try it after I get some work done.

What's max HT ref you've tried with the PC-AM2RD790 Achim?

[justapost]

Tried to add a third p-state between the other two at 2.3GHz also modified the max p-state value in an other msr register (see above).
In Desktop mode it is possible to set the p-state for an core by writing the p-state number into MSR C0010062h.

[justapost]

^Not tried it manually but the same thing happens if I remove the ">" prefix from the file.
I'll try it after I get some work done.

Debug that thing.

What's max HT ref you've tried with the PC-AM2RD790 Achim?

Was round 240MHz with 9500 have not tried max with 9600BE yet used 222MHz so far.

EDIT: few more scripts

cpu part of p-state 0 for core 0-3 is defined in Local0-Local3. Local4-Local7 are for p-state 1.

>Local0 = 0x280A
>Local1 = 0x280A
>Local2 = 0x280A
>Local3 = 0x280A
>Local4 = 0x6840
>Local5 = 0x6840
>Local6 = 0x6840
>Local7 = 0x6840
>cpu 1
>rdmsr 0xc0010064
>LocalA = and LocalA 0xffff0000
>LocalA = or LocalA Local0
>wrmsr 0xc0010064 LocalD LocalA
>rdmsr 0xc0010065
>LocalA = and LocalA 0xffff0000
>LocalA = or LocalA Local4
>wrmsr 0xc0010065 LocalD LocalA
>cpu 2
>rdmsr 0xc0010064
>LocalA = and LocalA 0xffff0000
>LocalA = or LocalA Local1
>wrmsr 0xc0010064 LocalD LocalA
>rdmsr 0xc0010065
>LocalA = and LocalA 0xffff0000
>LocalA = or LocalA Local5
>wrmsr 0xc0010065 LocalD LocalA
>cpu 3
>rdmsr 0xc0010064
>LocalA = and LocalA 0xffff0000
>LocalA = or LocalA Local2
>wrmsr 0xc0010064 LocalD LocalA
>rdmsr 0xc0010065
>LocalA = and LocalA 0xffff0000
>LocalA = or LocalA Local6
>wrmsr 0xc0010065 LocalD LocalA
>cpu 4
>rdmsr 0xc0010064
>LocalA = and LocalA 0xffff0000
>LocalA = or LocalA Local3
>wrmsr 0xc0010064 LocalD LocalA
>rdmsr 0xc0010065
>LocalA = and LocalA 0xffff0000
>LocalA = or LocalA Local7
>wrmsr 0xc0010065 LocalD LocalA
>rwexit

Force p-state 1 with actual settings (works best in Desktop mode).

>cpu 1
>wrmsr 0xc0010062 0 0
>cpu 2
>wrmsr 0xc0010062 0 0
>cpu 3
>wrmsr 0xc0010062 0 0
>cpu 4
>wrmsr 0xc0010062 0 0
>cpu 1
>wrmsr 0xc0010062 0 1
>cpu 2
>wrmsr 0xc0010062 0 1
>cpu 3
>wrmsr 0xc0010062 0 1
>cpu 4
>wrmsr 0xc0010062 0 1
>rwexit

Force p-state 0 with actual settings.

>cpu 1
>wrmsr 0xc0010062 0 1
>cpu 2
>wrmsr 0xc0010062 0 1
>cpu 3
>wrmsr 0xc0010062 0 1
>cpu 4
>wrmsr 0xc0010062 0 1
>cpu 1
>wrmsr 0xc0010062 0 0
>cpu 2
>wrmsr 0xc0010062 0 0
>cpu 3
>wrmsr 0xc0010062 0 0
>cpu 4
>wrmsr 0xc0010062 0 0
>rwexit

Those scripts work with cnq disabled and cpu vid set in the bios. Both p-states must work with your ref HT because an switch betwenn em is required to apply the new values.

[kwark]

Does anyone know what could cause the vcore to reset back to standard? Had it set to 1.475 which showed alright on cpu-z, but after running 3dmark it was back to 1.375 I'm using the DK 790FX M2RS by the way.

[justapost]

EDIT (updated above pic):
That above is lowest voltage for NB/CPU stable too, any lower it freezes.

I'm running near enough exact settings as you Achim, especially CPU settings. My system idles 108W AC @ this:
And with CnQ enabled now in the first pic above, it idles 94W AC (2x HDs, 2x 5V fans). Very good options to access and edit these registers IMHO, don't you think?

Yeah those p-states are great for tweaking, running with one HD and 3xFans atm.

CPU 2.6 (217x12) at 1.3V CPU VID
NB 2.17 (217x10) at 1.3V NB VID
MEM 578MHZ at 2.25V

idle: 157W AC
load: 270W AC

CPU .8 (217x4) at 1V CPU VID
NB 2.17 (217x10) at 1.3V NB VID
MEM 578MHZ at 2.25V

idle: 139W AC
load: 180W AC

Lowest possible consumption is cpu 200x4 at 0.9V nb 200x9 at 0.95V. In idle ~105W AC. So the board still needs more tweaking to beome more efficient.

A note aboute the NB multi. If CnQ is set to Auto in the Bios, the NB multi is always 9x. So it's required to up the ref HT to tune the nb.
However with above scripts it's possible to set the p-states and switch between em manual. Those work with CnQ disabled in bios.
A third p-state would be great, i'd like to have a low normal and high p-state.

Here are my settings I run with those two:

Current: MSR 0xC0010070
0x00000000 0x4800340A (1.100V NB/1.225V CPU)

P0: MSR 0xC0010064
0x800001BC 0x4800340A (1.100V NB/1.225V CPU)

P1: MSR 0xC0010065
0x80000187 0x48007040 (800/1800 0.850V/1.100V)

V above = VID.

As you can see, VIDs is how the processor controls all volts internally even for CPU and NB in all P-States including boot states. So that 1.250VID NB is 1.232V/1.240V. But NB VID never changed in P-State 1 unless you do this manually. I know NB FID cannot be changed after boot and that's why it won't change where HTC is active where GCLK downclocks nor when you have CnQ enabled but ... messing with the NB VID register it works fully, like so:

Is 2.6GHz stable at 1.225V VID?

I can change CPU DID to 1 and 2 real-time but anything higher is no go.
I've not tried NB DID yet.

The predefined p-states differ in the CPU DID and have the same CPU FID, can be it's faster to switch between the modes if only the DID changes.
NB DID must be equal on all cores's and p-states, no way to change the nb speed on the fly.

Yep, power is controlled by the CPU VID, NB VID, IddValue and IddDiv which also sets the TDP and that changes the Tcontrol and Tcontrol max limits apparently.

Have you played with IddValue/IddDiv? I assume it can be used to define under which load the 0 p-state get's used.
Do you know a stress-utility which can generate stress in steps? Maybe sandras energy efficiency test shows a difference.

BTW I know Tcontrol is not the actual temp value in degrees but just an arbitrary value to represent it. That's why it's allowed to read subzero at high ambients.

It's like i expected. calibrated against the worst case temp with arbitrary scaling.
Looking at the MSR registers HTC seems to be an feature of future steppings.

What happened was, my first 9500 which is the main one I experimented highly with temps, it read the temp in BIOS the same as the physical Tcase temp most likely because it was missing the offset, but the ones after that were all different. This 9600BE reads the register properly (sub-ambients).

Same with F3xA4, I asked about it because on the NB register access it read 0b for me so I thought there's another way. It reads correctly now but many times it blanks out or reads F's.

In terms of temps i rely on the external sensor on the mobo. This one reports the highest temps. The avreage is +10° over CPU temp. A probe next to the prozessor reads the same temps as the cpu sensor most of the time, so i assume this temp is actualy higher.

Thanks for adding the bits, makes me not have to read the guide. Although you did make me read up the guide once again you know...

Skimmed over the whole thing one time, just to get an outline and know where to look for what. Alot of extra research is required on my side to read that doc.

[Undersea]

Does anyone know what could cause the vcore to reset back to standard? Had it set to 1.475 which showed alright on cpu-z, but after running 3dmark it was back to 1.375 I'm using the DK 790FX M2RS by the way.

Overdrive?

[serial099]

so, finally got my 790fx-m2r m/b back from dfi RMA (actually I got it last week, but didn't get a chance to check it out (due to my crazy schedule). Anyway, I received it back from dfi RMA with the same indications (C1 stop error if memory slots are in #3 or #4 are occupied). It looks to me like the BIOS chip was changed out (wrote the numbers off of the old one) and they put a new revision code sticker on there (was R.AC0 before and now it's R.AD0) but other than that it looks the same....maybe they changed something and it didn't work, but who knows for sure.

[KTE]

kwark: AOD can do that, yup.

Achim: I'll check out those scripts when I get time. Been too busy yet.
Lowest I've had stable which is also my max stable yet (without freezes) is what I'm running since my last post.





Idle is still 94W but load is now lower. 186W P95 Small FFT.
Now typing in Firefox, 6 tabs open, with AV/FW engines running, AMD Power Mon and two text files open, I'm idling 96W AC.
P95/bench/firefox is all fine, just have to test a memory intensive game yet. First benchmark for L3 instability is EVEREST L3 bench. It will lock up if totally instable. The next best usually is rendering and better is a game. I've done some Apophysis fractal rendering fine. Next is a game.

It's been up for over 24hours so far without a problem. Problem for me is not P95 stability, that's quite easy. First 4 weeks 2.7GHz was 1.25V stable. The problem for me is avoiding the freeze after a day to three days idling. So far this is best yet. CPU seems to love low voltages over high ones.

Running 1.225VID because I can then access lower voltages below 1.264V but above 1.24V. Like right now Idle vs. Load =>

vs.

Yeah those p-states are great for tweaking, running with one HD and 3xFans atm.

CPU 2.6 (217x12) at 1.3V CPU VID
NB 2.17 (217x10) at 1.3V NB VID
MEM 578MHZ at 2.25V

idle: 157W AC
load: 270W AC

CPU .8 (217x4) at 1V CPU VID
NB 2.17 (217x10) at 1.3V NB VID
MEM 578MHZ at 2.25V

idle: 139W AC
load: 180W AC

Wow, big differences to mine and we're at similar MHz. Maybe it's the PSU efficiency giving those results? Actually you have 578 2.25V on MEM, and I have 536 2.16V. That's only maximum 3W DC more though. You also have a high HT ref. compared to mine (201) and my NB is low, 1.038 in P-State 1 and 1.038 in P-State 0. Previously max I've had stable at 1800MHz IMC was 1.050VID 1800 at 1.27V 2.7GHz CPU. I also run HT at 1.2V. It looks like I must be running lower current than you are, only that can explain the huge difference (almost 100W AC load).

These MSI BIOSes don't have VID options in BIOS (apart from old 1.13B).

Through testing I previously found, CnQ with low CPU VID/Voltage won't get much gains in dropping power compared to how much you gain by just dropping NB VID/Volts. I get quite a bit of gain by dropping NB VID/Volts, it is supposed to be a power hog which we knew since around June, and you can see that clearly. I have ran 2.211GHz max on 1.250VID NB stable so far, haven't tried more.

Make note: This was no way possible in first 3 weeks. 2GHz NB at 1.250V in them weeks would reboot.

Lowest possible consumption is cpu 200x4 at 0.9V nb 200x9 at 0.95V. In idle ~105W AC. So the board still needs more tweaking to beome more efficient.

A note aboute the NB multi. If CnQ is set to Auto in the Bios, the NB multi is always 9x. So it's required to up the ref HT to tune the nb.
However with above scripts it's possible to set the p-states and switch between em manual. Those work with CnQ disabled in bios.
A third p-state would be great, i'd like to have a low normal and high p-state.

If CnQ is disabled how do those scripts change between P-States and when?

Is 2.6GHz stable at 1.225V VID?

See above, yep. VCore is higher, 1.248V idle, 1.240V load. I'm surprised myself. 2.639GHz froze idling after 2 days at even 1.3-1.48VCore. I only recently started trying these lower volts.

The predefined p-states differ in the CPU DID and have the same CPU FID, can be it's faster to switch between the modes if only the DID changes.
NB DID must be equal on all cores's and p-states, no way to change the nb speed on the fly.

Yeah, I've switched CPU FID and DID with P-States and manually in Windows. But not NB DID/FID, no way as guide mentions.

Have you played with IddValue/IddDiv? I assume it can be used to define under which load the 0 p-state get's used.

I haven't, no. Is that register write enabled or only read? I thought it was auto set.

Do you know a stress-utility which can generate stress in steps? Maybe sandras energy efficiency test shows a difference.

I don't really. Only one I recall is Intel TAT which does this. You can always go old skool and use

int main()
{
    while (true);
}

...then just customize further and have four of them open to stress.

I'll tell you what I use though. I use this utility I've attached. Can choose to stress different cores with it (can set affinity manually to get different cores and different loads). Works good, not Prime95 load, because those iterations are FPU intensive and this isn't, but it produces a variety of load and priority is set to 4 (IIRC), so it won't jam your screen apps unusable. It's probably the first test I use each time. It still doesn't go up in steps though.

It's like i expected. calibrated against the worst case temp with arbitrary scaling.
Looking at the MSR registers HTC seems to be an feature of future steppings.

The real TCASE temp actually is the same as the TCONTROL value we get at one point near 60C according to graph given in BKDG. But what is funny is that TCONTROL is supposed to be lower all the way than the actual TCASE temp until a certain intersection point whereby TCONTROL becomes higher than the real TCASE temp (IHS temp). So you guys seeing high temps at some point under load but low temps idle get everything reported correctly.

In terms of temps i rely on the external sensor on the mobo. This one reports the highest temps. The avreage is +10° over CPU temp. A probe next to the prozessor reads the same temps as the cpu sensor most of the time, so i assume this temp is actually higher.

Yea true, Internal core temp will always be higher than TCASE temp (IHS). Usually minimum 15C higher.

Skimmed over the whole thing one time, just to get an outline and know where to look for what. Alot of extra research is required on my side to read that doc.

Hehe, you know the last guides were easier to read and make sense of than this one. I've heard many developers confused by this one and complain.

[KTE]

Found my lowest stable settings:

CPU 201x12 1.225VID/1.248V lowest
IMC 201x9 1.038VID lowest

Power idle: 92W AC
Power load: 181W AC

But you can increase this further. I'm on this now at the same volts=>





Power idle: 94W AC
Power load: 192W AC

Big jump but I'm quiet happy.

[justapost]

Had the 3850 in my system yesterday, forgottt that in my specs. ALso had upped the chipset voltages. Here's what i can use save with stock ref HT.

MOBO: Sapphire Clone - SB 1,2V/NBc 1,12V/NBpcie 1,12V/NBht 1,04V
Note: Audio+Modem Card's coming with mobo attached and only one 4pin 12V connector used.

PROC: 9600BE
MEM: 2x1GB CB Tracers 6400 @ 1,8V 800MHZ 5-5-5-15
GFX: HD2600XT @ stock
COOLER: BigTyphoon 120 with 120mm ixtrema fan on zalman fanmate on lowest speed, 1xAMD stock cooler fan for PWM.
PSU: ZM460B-APS
HD: 1xWD1600YS 160GB SataII RE
DVD: LG-GSA10N IDE

p-state-0:
cpu: 13x 1.3V VID
nb: 9x 1.1V VID





idle: 126W AC / 100,7W DC
load: 230W AC / 187,5W DC

pstate-1:
cpu: 4x 0.9V VID
nb: 9x 1.1V VID





idle: 108W AC / 85,3W DC
load: 127W AC / 101,5W DC

If you disable CnQ in the bios you can still customize the two p-states for each core and force the settings to load by switching to that p-state via writing the p-state number to MSR register C0010062h.
Therefore I added two scripts whom set pstate 0 and the 1 or vice versa 1 and the 0.
If you are in p-state 0 writing 0 to C0010062h does not update the settings, so i have to switch to state 1 and back to state 0.

Thank you for attaching that stress utility. Unfortunately the attachment does not work.

What efficiency does your PSU have at 100W? Mine 100W ~78,6% 110W ~79%.

EDIT: Looking at my screenies i realize that prime95 failed on one core so i still need above 1.3V CPU VID to run stable.

[KTE]

Ah ok. Yes, that's true, you can customize MSR[...]62 to switch P-State manually without CnQ.
You don't need to disable CnQ in BIOS though, just change Power Options to Max battery and try in Windows.

I haven't tried checking CnQ settings load watts. [added below]

Scripts don't work for me still. Debugging doesn't get far. RWE just freezes and you have to use Task Manager to kill it. Will need more time for it.

Your 1st power figures (2600) should read AC / DC.. you missed that but edit comes handy

You'll need more than 1.312V for 2600 P95 stable it seems. I'll update mine to a similar setup and then try and compare power consumption and work out why the difference. I'll use your volts and settings. I'll do it on this now and then with the Sapphire when I get hold of one (should be soon).

115V: PSU is 78.5% eff. at 110W AC and 81% eff. at 156-186W AC.
220V: PSU is 80.6% eff. at 110W AC and 84.3% eff. at 156-186W AC.

I'm going to pick up the Gigabyte GE-S550A-D1 PSU soon and use it's P-Tuner software which is pretty damn accurate (known problem is +25W DC showing and 12V3+ below 180W DC is wrong) to show me the amps/volts each rail is pulling and work out the DC power draw by the CPU 8-pin.

So we'll know what the CPU is actually pulling alone and I'll put the GPU/MB/peripherals on separate 12V rails so we can work their draw out too.

The attachment linked worked before but doesn't now
Attached it again anyway.

EDIT:
I just tried everything again, found a bug in CnQ. Good news.

1. 
CPU 202 12x 2.626GHz @ 1.248V, 1.225VID
NB 9x 1.818GHz @ 1.038VID
HT 9x 1.818GHz @ 1.2V
2x 1GB RAM 538 5-5-5-18-20-75 2T @ 2.1V 1.25x all DS
Fan1 1510RPM @ 5V 400mA (stock) / 2300RPM load @ 7V
Fan2 810RPM @ 5V (120mm)
Sapphire HD 2600 XT 800/700 @ 1.26V/DK
32-47% GPU fanspeed
1x SATA II WD Caviar SE 76GB
2x USB ports (mouse/keyboard)
1x Gbit Ethernet port
Antec Earthwatts 430W

Power: 105W AC idle, 184W AC load
Power: 84.6W DC idle, 155W DC load

2.
CPU 202 4x 0.808GHz @ 0.864V, 0.850VID
NB 9x 1.818GHz @ 1.038VID
HT 9x 1.818GHz @ 1.2V
2x 1GB Tracer RAM 538 5-5-5-18-20-75 2T @ 2.1V 1.25x all DS
Fan1 1510RPM @ 5V 400mA (stock)
Fan2 810RPM @ 5V (120mm)
Sapphire HD 2600 XT 800/700 @ 1.26V/DK
32-47% GPU fanspeed
1x SATA II WD Caviar SE 76GB
2x USB ports (mouse/keyboard)
1x Gbit Ethernet port
Antec Earthwatts 430W

Power: 87W AC idle, 98W AC load
Power: 67.5W DC idle, 76W DC load

90W AC consistent right now with basic apps running.

Compare power draws of this same system under different specs before:
15th January: http://www.xtremesystems.org/forums/...&postcount=693
25th January: http://www.xtremesystems.org/forums/...&postcount=839
1st February: http://www.xtremesystems.org/forums/...&postcount=950

[Oese]

Interesting things you're discussing here.. I'm not through with this thread as a whole so I dont know if the p-state-discussion evolved out of phenom problems or these are just nice possibilities to hold down your power consumption.. whatever, will get to learn that later..

I myself own the Board for about 2 weeks now and there are two questions remaining (specs in signature soon):

I can't run > 300mhz htt with integer cpu-multiplier (for example 10x) @ DDR667-Divider, no matter which ht-multi-setting, although CPU was successfully testet with prime @ 280x12 @ 800Mhz ht-multi, highest achievable ram speed ist 266x12 @ DDR800-Divider (so 1066) @ 1Ghz HTT prime stable..

> 300Mhz up to at least 340mhz htt is no problem with half cpu-multipliers (i.e. 10.5x) @ DDR667 ram speed - funny? I would be pleased, but ram performance is about half at half cpu-multipliers.. And theres no tref option or anything...

Suggestions/Answers? I'm just wondering.

I think it's the imc of my cpu, but would appreciate to hear your opinions..

If I got it right, cpu host/htt boot up clock can remain at 200mhz when playing with the cpu multi.. did not encounter any better behaviour if I set it to 266, which is the highest bootable setting with default 12x multi..

second question is could i do anything about my imc/ram related oc-problems with dram driver settings? I'm used to timings and dram data drive strenght, dram drive strength so far, but not one page of driver settings although i any additional setting to play around with is welcome given good stability at optimized defaults, which this board definitely has..

any suggestions for playing around with these settings? weak/normal drive (i know since dfi nf3 ultra-D ) have been already testet, so are the "normal" timings.. I can't get past 1066 substancially with my powerchip-based GSkill GBPQ.. I think 1100 would be possible if my imc wouldn't be that crappy..

Many thanks

[Oese]

signature... aah forgot: bios is 08/02/12 beta... same issues with 08/01/30 final..