Intel's First Nehalem Cpu-Z Pic.

[Zytek_Fan]

Not yet, as he even says himself it reads some parts wrong.

I still dont believe in a L3. It simply makes no sense when looking on the size and past history. Itanium only got a L3 due to the massive sizes of up to 24MB and soon 30MB. And I dont think anyone here on the board got access to a nehalem system, nor will have it for the next 3-6 months.

L3 is a step backwards for mainstream, not upwards.

http://en.wikipedia.org/wiki/Nehalem...rchitecture%29

Nehalem will come in variants for servers, desktops, and notebooks. The processor for four-socket servers is codenamed Beckton, the chip for two-socket servers Gainstown, and the chip for single-socket desktops is Bloomfield [6].

According to DailyTech, all models of the desktop chip Bloomfield will have three DDR3 channels. The quad core models will have 8 MB of shared L3 cache (Penryn has 12 MB of semi-shared L2 cache), and the high-end models will have a 130 W TDP, compared to 136 W for high-end Penryns[5]. Desktop Nehalem processors will use either Socket LGA715 (Socket H) (according to DailyTech's Kristopher Kubicki) or Socket LGA1160 (according to PC Watch). Kubicki has stated that either he or PC Watch could have old documents. Server processors will use the LGA1366 socket with support for registered DDR3[6].

Seven codenames have been associated with the Nehalem microarchitecture in a PC Watch article. These include two server processors, three desktop processors, and two mobile processors. The server processor, Beckton, will have 44 bits of physical memory address and 48 bits of virtual memory address.

A HKEPC article [7] states that Nehalem is Penryn with microarchitectural and power efficiency improvements, including better lower power states and leakage reduction. Nehalem will, compared to Penryn, have 1.1x to 1.25x the single-threaded performance, 1.2x to 2x the multithreaded performance, 30% lower power usage for the same performance, and higher performance for the same power usage. It also states that Nehalem will have a "turbo mode" that enables cores to run at faster speeds than the TDP rated speed. Due to its early release and market segment, Bloomfield will not have an integrated memory controller, but it will still have QuickPath Interconnect. Its corresponding Tylersburg chipset supports dual channel and triple channel RAM, and a maximum of 24 GB RAM. Tylersburg will also support Quad CrossFireX.

[informal]

I think Shintai owes 100E to a lot of people on the board...

Thanks for the insightful post and explaining how the new chip will work!

I propose we send him details for delivering the money .Let's see,100e x approx. 100 members who've read his post =hot damn 10K euros .

[Shintai]

http://en.wikipedia.org/wiki/Nehalem...rchitecture%29

Please dont link to the Wiki. its usually more wrong than right. Its the collective wisdom or stupidity.

May I remind you of this:

http://en.wikipedia.org/wiki/Wikiped...ral_disclaimer

Wikipedia is an online open-content collaborative encyclopedia, that is, a voluntary association of individuals and groups working to develop a common resource of human knowledge. The structure of the project allows anyone with an Internet connection to alter its content. Please be advised that nothing found here has necessarily been reviewed by people with the expertise required to provide you with complete, accurate or reliable information.

That is not to say that you will not find valuable and accurate information in Wikipedia; much of the time you will. However, Wikipedia cannot guarantee the validity of the information found here. The content of any given article may recently have been changed, vandalized or altered by someone whose opinion does not correspond with the state of knowledge in the relevant fields.

[Shintai]

I propose we send him details for delivering the money .Let's see,100e x approx. 100 members who've read his post =hot damn 10K euros .

Ye sure, just remember to send the official/validated information about nehalem aswell.

[Ugly n Grey]

I think this is going to bite you in the ass Shintai. You'll coast for a while as no one is going to break NDA. Good luck.

[Craftyman.]

Care to speculate on overclocking potential? Will it be slightly better or worse do you think with integrated PCIe??

[ghost101]

Please dont link to the Wiki. its usually more wrong than right. Its the collective wisdom or stupidity.

Right...

So what your saying is that because some things are sometimes wrong, we shouldnt trust it. I'd like you to give me an information database which is 100% accurate.

Yes, wikipedia is vandalised and sometimes people screw with some articles due to controversy and/or biases. Also, wikipedia touches on subjects retail encyclopaedias wouldnt touch with a barge pole. However, i don't really think this article is victim such people. Besides, it clearly cites its sources.

If you adamantly feel something is wrong, correct it with some evidence.

[Shintai]

Right...

So what your saying is that because some things are sometimes wrong, we shouldnt trust it. I'd like you to give me an information database which is 100% accurate.

Yes, wikipedia is vandalised and sometimes people screw with some articles due to controversy and/or biases. Also, wikipedia touches on subjects retail encyclopaedias wouldnt touch with a barge pole. However, i don't really think this article is victim such people. Besides, it clearly cites its sources.

If you adamantly feel something is wrong, correct it with some evidence.

See thats the issue. The Wiki right now for Nehalem is no more than a sum of some of the rumours that is around. For an example, try see how the Phenom/K10 Wiki article looked like before the product was out.

[cegras]

See thats the issue. The Wiki right now for Nehalem is no more than a sum of some of the rumours that is around. For an example, try see how the Phenom/K10 Wiki article looked like before the product was out.

You just answered your own question.

I hereby introduce the GIGO principle:

Garbage In; Garbage Out.

Don't speculate or formulate on rumours?

[terrace215]

A shared L3 between 4 cores means highly complex arbitration mechanism ( that equals increased latency ).Look at AMD's K10 L3.Nothing to brag about either.It is slow , very slow.

With such small L2s , how can they feed a highly complex core with 2 threads ?? Multiple threads means cache thrashing , small size amplifies that and you have a slow L3 behind it.
If that's a good cache subsystem , I'm stupefied.It goes against everything Intel has done lately ( large , shared , extremely fast L2s which thrashed IMC equipped CPUs ).

What about the FSB ? DP Nehalem uses QPI , that works at speed of up to 4.8GTs.How does CPU-Z read that ?

This is more rubbish.

You've been more than corrected on the other forum you took this FUD too:

http://investorshub.advfn.com/boARDS...ge_id=26502149

Amazing ignorance.

[terrace215]

6MB L3 actually. I believe L2 will stay at 512kb per core. 256k is a bit low for L2 cache. If its true savantu might very well be right on this one(instruction cache only).

I thought SpecFP/Int_rate are bandwidth benchmarks
Needless to say just having an IMC and QPI would boost "rate" benchmarks significantly and does not imply better single thread performance.

Yes, that's why I used the phrasing, "Then there is". It's ANOTHER claim by Intel regarding single thread IPC. They've claimed that BOTH single thread IPC will be better, AND we have the int/fp_rate improvement claims. As well as a general "bigger performance jump from Penryn to Nehalem than from Netburst to Core2".

The silly thing here is savantu imagining that Intel designers have not simulated the performance of their cache heirarchy to death, so that he knows better, and can pronounce it flawed, with virtually no data! His retort seems to be, "well, Intel engineers designed Netburst once, so they suck."

Yeah, right.

[adamsleath]

cant wait t0 hear real specs from intel (or 'other' independant reliable source)
vs spec ulation that is

cf GIGO.

[socket]

screen of CPU-Z is fake imho.

i need real photo of real CPU with 1366 LGA pins.

exist only one photo:

[hollo]

2 threads through a 256kb cache?
maybe they decided single threaded performance wasn't the highest priority for this architecture.. or maybe there's been a significant latency improvement with the 45nm process... because 1 thread through 256kb is a bottleneck on l2 caches as we know them, let alone 2 threads.

it's sad for single-threaded performance, but
programs that need high performance have to be multithreaded to get it these days

The numbers given by CPU-Z kinda makes sense to me from the insignificant sources I have.

To me, it wouldn't make sense to test both QP and a new architecture together at present time, as they are both independent technologies. Could be me, but testing QP with a proved CPU + testing Nehalem with a proved FSB / connection is sensible. When both are satisfactory in terms of expectations, then the tests of combining them could begin. Just don't makes sense to test multiple new technologies all at the same time, as problem / error finding complexity increases.

Just speculating, of course, as I really don't have any insights into how the protocol is for testing these kinda of things.

could be, the nehalem demo'd at IDF was in LGA775 package so nehalem on front-side-bus definitely exists http://www.theinquirer.net/en/inquir...lem-pixellated

[Spawne32]

I cant wait for nehalem, im holding off on penryn just for this reason. It will be great to see some real pictures when they do surface in a few months.

[Shintai]

could be, the nehalem demo'd at IDF was in LGA775 package so nehalem on front-side-bus definitely exists http://www.theinquirer.net/en/inquir...lem-pixellated

I say theinq was just guessing I bet. Nehalem cant fit into a LGA775 for a few reasons. One is the IMC, other part is FSB doesnt exist at all along with changed electrical properties. It was a LGA1366 or LGA1160. (LGA1366 most likely since they demo DP setup).

If you also notice they only show the front of the chips.

[mstp2009]

Contacted a buddy in D1D at Oregon about this SS and for what Nehalem info I could get out of him.

He says:
1) not a fake, but CPU-Z is off on several things (he won't tell exactly what)
2) Nehalem boots and runs stable under load on all major OSes
3) Intel could have it "rushed" to market in 2 months if need be, but they don't feel the competitive pressure to do so (thanks AMD).
4) most of what is being worked on now are the chipsets for the various platforms (desktop, server, etc.)



And yes Shintai, this is all on just my word. So don't bother thread crapping my post, time will prove one (or both of us) right.

[onewingedangel]

Once spring IDF rolls around I have a feeling a lot of our questions will be answered, perhaps some we haven't yet thought of

[Blauhung]

Care to speculate on overclocking potential? Will it be slightly better or worse do you think with integrated PCIe??

I would venture a guess that the locked multi intigrated PCI mainstream chips will not overclock nearly as well as we are seeing right now with the current mainstream offerings.

First off, the community currently has no idea how well the new QPI will scale. of course with high multipliers against the QPI, there is the possibility it won't need to scale much, but that's up in the air right now. Second, we don't know how the memory speed will be linked to the QPI speed and there could be another point that hinders the available headroom. Both of these factors will hit all of the Nehalem type chips.

For the mainstream ones, you take the above mentioned unknowns and tack on integrated PCIe, there's another portion of the same die that will have to somehow recieve a clock signal. It's possible that this core clock signal is also based off of to the QPI frequency, so if the headroom on the PCIe portion of the chip may end up being a limiting factor.

There are many ways that all of these can be handled, but I believe that the mainstream side of things will take the tact of simplicity over tweakability.

Edit: although, i think we must keep in mind, even though they may not overclock as well, they will be faster then their penryn equivalents. The question becomes, is there enough headroom on the mainstream chips to put a maxed out mainstream Nehalem (lynnfield) over a maxed out quad core penryn? Only time will tell on that.

[dinos22]

I think this is going to bite you in the ass Shintai. You'll coast for a while as no one is going to break NDA. Good luck.

he's not letting up is he

lines up to collect 100E as well

[Shintai]

Intel kinda thought differently with the Gallatin P4 EE back in the days, didn't they? AMD with its Phenoms also thinks differently at present time. L3 isn't only a thing for servers, and not something without benefits for non-servers.

L3 is a substitute for the size you cant make the L2. Just as the L2 is the same for the L1. Or main memory is for L2/L3 etc.

In the Gallatin it was used to give a small boost, but at a big price. AMD is abit different since its stuck to the way they made their quadcore design and "lacked" cache knowhow if you can say that.

So a L3 only makes sense if you cant make the same size in a L2. It could be 8MB L2 is too much for Intel, but looking on the 6MB on penryn...

Another example is current Core 2 Xeon offerings, including MP have been completely ridden of L3.

I think many want Nehalem to be a K10 copy in design.

[Ugly n Grey]

I think many want Nehalem to be a K10 copy in design.

Not quite accurate.... just think about the fact that chip design is migrating to having many cores cooperate with each other as quickly as possible whether they be on die or off. Now think about the steps involved in moving platforms towards this goal, whether server or consumer. You end up with designs that aren't going to be that far apart theoretically. Of course execution is everything and Intel is executing very well indeed..

[BrownTown]

Some of the cache numbers just don't make sense to me. Like them redicing the size of the L1 data cache is kind of weird. The 8MB of L3 is consistent with what we have seen, however I was of the understanding that the L2 was 512kb not 256. Looking at the die shot the ratio of the L2 and L3 sizes would clearly indicate 512kb of L2. Also the FSB stuff looks all wrong, but I guess since they would have to be using some prototype motherboard then it makes sense that the FSB isn't up to full speed yet.

[Vapor]

(not to Browntone...just happens to be placed after his post)

Shintai, L3 is just the third level of cache. Says nothing about its performance...

What's stopping it from being nearly identically performing and configured as Core 2's L2 is right now? Maybe Intel wanted another level between Core 2's L1 and L2. Can't call it L1.5...so you bump L2 to L3 and put your new small cache in as L2.

[Zytek_Fan]

(not to Browntone...just happens to be placed after his post)

Shintai, L3 is just the third level of cache. Says nothing about its performance...

What's stopping it from being nearly identically performing and configured as Core 2's L2 is right now? Maybe Intel wanted another level between Core 2's L1 and L2. Can't call it L1.5...so you bump L2 to L3 and put your new small cache in as L2.

QFT!