Computex 2019 - AMD teased new Ryzens 3. gen (launch 7.7.2019)

[vario]

I think that KF is going to be over 200W for 5ghz all core on any reasonable load. You also have to consider how turbo works on both platforms. XFR does not respect any TDP so long as the board/cooler are good enough, and in spec turbo is almost useless. The KF is still a 95W part on ARK, so other than the warranty on 5ghz all core you are not really getting anything without overclocking. Anyone doing a proper bench without overclocking and in official spec then would have a hamstrung KF doing about 105W, and the 3800x on a good board with a good cooler will be rocking 250-300W in spec if it needs it, but on a garbage board or cooler will be doing the same kind of much lower clocks and ~100W that the KF is doing. The 3800x is shipping a 160W wraith prism cooler, so it would never really work out to compare them with both being "in spec" and "not overclocked."



I dont have a source for that, but I did talk a rep about epyc last year and they were talking about next gen having some cache on a routing chip to help with cross die latency. It seems like this would be the application if it is going to be a thing. I want to go through the white papers when they come out with the launch.

I dont know man, i dont think they were comparing them overclocked, remember this showcase few months back when they were showing 8 core zen 2(no model number then) vs 9900K in cinebench ?
They had the same scores, but power usage on zen 2 and 9900K was in spec , and lower on zen2 than 9900K.
There are limits to auto oc using xfr/pbo and on the intel sie mce also there are turbo durations that SHOULD be respected.
TDP on intels site is coolers capacity more than real power consumption tho.

As for the IO die, yes, the one for EPYC is diffrent, its so big it can have cache on it.But it would simply not fit on am4 package. From what ive seen, for Am4 there is one IO die, the same for 1 and 2 chiplet cpus.

[zanzabar]

As for the IO die, yes, the one for EPYC is diffrent, its so big it can have cache on it.But it would simply not fit on am4 package. From what ive seen, for Am4 there is one IO die, the same for 1 and 2 chiplet cpus.

It sounded like epyc and ryzen 2 would the same but double the parts (4 cpu die, 2 IO die, with them being the same or very similar.) That is why I want those white papers. It might turn out that the cores have the same cache as before, but the IO chip doubles it for each cpu die connected.

If it was like that then I dont see how you get the 64/128 lane PCI-e.

[vario]

It sounded like epyc and ryzen 2 would the same but double the parts (4 cpu die, 2 IO die, with them being the same or very similar.) That is why I want those white papers. It might turn out that the cores have the same cache as before, but the IO chip doubles it for each cpu die connected.

If it was like that then I dont see how you get the 64/128 lane PCI-e.

Im not sure i understood you correctly.So im just gonna post pics .
Thats Epyc 2, it has 8 chiplets and one huge IO die:
https://images.anandtech.com/doci/13...78_678x452.png

Thats Ryzen 3000 8 Core one:
https://cdn.wccftech.com/wp-content/...en-3rd-Gen.jpg

And thats Ryzen 3000 12 core one base on 2x eight core chiplets.
https://images.anandtech.com/doci/14...ar_678x452.jpg

The dimensions of RYZEN`s IO die, are pretty much very similar what you would get if you took zen zeppelin die and removed cores+cache, as it is still based at 14nm, no shrinkage.So i really doubt that they managed to cram more cache in there.
But as you see, the epyc IO die is massive in comparison, so i dont know .