New Memory Tweaker for Intel Chipsets

[DualCpuUser]

That's my problem on Vista x64, displays and that's it with 35beta.

Oh and put a link on your website to get/try the beta's.

Ty

[FELIX]

and what is the problem?

[Hazzan]

I cant use memset 3.5beta.... like crash on memset, only work double click shortcut and exit on tab in memset..

[FELIX]

...when Apply and Save button isn't show, it's cause the MCHBAR is locked in Write.
You can check it by: Open WPCRedit on PCIBus :0 Device:0 Function:0 and look at
OffSet F4, bit[0] :if it's at 1, MCHBAR have been locked in write by the bios.
And unfortunately, it's a "read only" bit, You can't write 0 in this bit.

[farookh]

...when Apply and Save button isn't show, it's cause the MCHBAR is locked in Write.
You can check it by: Open WPCRedit on PCIBus :0 Device:0 Function:0 and look at
OffSet F4, bit[0] :if it's at 1, MCHBAR have been locked in write by the bios.
And unfortunately, it's a "read only" bit, You can't write 0 in this bit.

Felix is there ne way to open the F4 bit its set to read only on the ix38 quadgt
Shows up as MCHBAR locked in memset 3.5beta

[georgesod]

Abit ip35pro latest beta bios. It doesn't work as usual

[JacKz5o]

Nice find, works well.

[pijany]

works really great on my abit nf-7s whit a-data vitesta pc4000.
I'm testing beta for now it's stable for me. next week i'll get new memory and mobo we will see
Good job Felix

[xgman]

I can run 3.4 fine, but 3.5 says "unable to execute file in temporary directory" Error 5 Access Denied" when I click on the downloaded file. Any ideas why?

I moved it to an empty folder and then it ran the setup.

[msgclb]

Felix here's MemSet 3.5 beta on my EVGA 780i. Has it been updated for the 780i chipset or is it normal to see NVIDIA NForce 680i SLI?

[FELIX]

->xgman: no idea, perhaps cause the executable file is not in a good folder...

->msgclb: I know this "problem", cause 680 and 780 have the same device ID, Same thing with X38 and X48:
I need to find an other way for identified these chipsets...

[HKPolice]

I have an Asus Commando + Windows XP64bit and the performance level setting doesn't seem to work! Default is 12, I set it to 6 and it doesn't make any difference in Everest Latency or Memory Read benchmark. Still stuck at ~8900MB and 59.3ns.

Any ideas? Running 490FSB 1:1 with 4x1GB sticks 4-4-4-15 timings.

[RaceBannon]

Felix, are you trying to get Performance Level/Read Delay to work on P965 boards?

[necron66]

This is probly nothing, but noticed last night memset is reading mem speed differently to what it is. I don't notice this on XP, only on vista.

[FELIX]

Performance Level/Read Delay work with some P965 chipsets, but not all, and I don't know why.

[fgw]

Performance Level/Read Delay work with some P965 chipsets, but not all, and I don't know why.

felix, i'm currently looking into squeezing out my memory and found it interesting that on my ab9quadgt (p965) i get two different performance levels on the two dimms! for one dimm memset 3.5 beta reads 9 for the other it reads 10!

the only program i could get hold of by now, which allows me to check this settings is memtest. i modified the code to read all required timings off the mch!

anyway, as it's not clear to me from looking into the data sheet where to find some timings i ask you if you can help me here.

i'm looking for the following timings for the p965 chipset:

tPALL_RP (All Precharge to Activate): 252h [9:12]
Performance Level: 250h [2:5]
tWR (Write to Precharge Delay): 250h [6:10]
tRTP (Read to Precharge Delay): ???????
All Precharge to Refresh Delay: 25Bh [9:12]
Command Rate: ???????

this are the registers and bitpositions i used. could you pls check your code or documents to verify if my locations are correct?

thanks

[Nosfer@tu]

Minor error there.
Problem has been there for some time. But who cares

[LuckMan212]

Hello,
I have a problem/question:
I am trying to tweak my memory timings, but I am not sure I understand why different text terms/labels are used in SPD section vs. the main section? It makes it hard to know which #s to tweak because for example Row to Row delay exist on SPD side but not in main window. Er, Im sure it exist but which one is it??

I am on a e6850, gigabyte p35 btw. vista 32.

[FELIX]

It's cause I use name peculiar to each datasheet, so in spd documentation, is Row to Row Delay,
and in Intel doc. is Activate to Activate Delay;

-Write to Precharge delay = Cas# + 3 + Write Recovery time(spd)
-Write to Read (main) = Cas# + 3 + Write to Read(spd)
-Refresh Period (main) in clock = Refresh Rate(spd) in µs

[Signal64]

I am trying to tweak my memory timings, but I am not sure I understand why different text terms/labels are used...

It's cause I use name peculiar to each datasheet, so in spd documentation, is Row to Row Delay,
and in Intel doc. is Activate to Activate Delay;

-Write to Precharge delay = Cas# + 3 + Write Recovery time(spd)
-Write to Read (main) = Cas# + 3 + Write to Read(spd)
-Refresh Period (main) in clock = Refresh Rate(spd) in µs

FELIX - I'm trying to "translate" SPD, BIOS, and MemSet readings on a P35 as well. I fully understand why the terminology is used in MemSet and just wanted to make sure I understand a couple of items:

Sorry if this is remedial or obvious, just like to be sure.

-Write to Precharge delay = tCL + 3 + tWR
-Write to Read Delayed = tCL + 3 + tWTR

Would that be accurate?
You mentioned (spd), but if tWR and tWTR is able to be set in BIOS that is still used instead of spd, correct?

MemSet
RAS# to CAS# Read Delay
RAS# to CAS# Write Delay

Both of these can typically be from a "RAS# to CAS# Delay (tRCD)" setting?

MemSet
Read to Write Delay (tRD_WR)

This is also referred to as tWR?

And tRC is not used at all as P35 MCH doesn't have or use it, correct?

[FELIX]

Is the Performance Level, in any Intel documentation?

No.

Is there a dos version of a similar program?

No.

-Write to Precharge delay = tCL + 3 + tWR
-Write to Read Delayed = tCL + 3 + tWTR

real equation is:
*Write to Precharge delay = WRITE Cas# Latency + (Burst Lengh / 2) + tWR
-Write# Cas Latency= Read Cas# Latency(tCL) - 1;
-Burst Lenght: Practicaly always = 8;

so:Write to Precharge delay = tCL - 1 + (8 / 2) + tWR = tCL + 3 + tWR

*Same for tWTR

Would that be accurate?

these equation are indicate in Intel datasheet;

You mentioned (spd), but if tWR and tWTR is able to be set in
BIOS that is still used instead of spd, correct?

yes and no: some BIOS not show correctly these values

Both of these can typically be from a "RAS# to CAS# Delay (tRCD)" setting?

Yes.

Read to Write Delay (tRD_WR)
This is also referred to as tWR?

No, but the best is you to read datasheet at page 135 and above...

[RPGWiZaRD]

Is there anyway to bypass that locked MCHBAR thingie without having to use that tool listed in first post as it's not too convenient to use as I don't understand addresses and such anyways to make it practical. Locked MCHBAR is the only thing that bothers me having switched to a Abit IP35 Pro.

[FELIX]

Is there anyway to bypass that locked MCHBAR thingie without having to use that tool listed in first post as it's not too convenient to use as I don't understand addresses and such anyways to make it practical. Locked MCHBAR is the only thing that bothers me having switched to a Abit IP35 Pro.

...is it writing "MCHBAR Locked" on memset?
If it is, your MCHBAR is locked in Bus 0 Dev 0 Fct 0 ,OffSet F4h, bit [0];
If bit[0]=1, your MCHBAR is locked, and is not possible to reset this bit under windows.

[FELIX]

->necron66: if you find a difference in memset reading frequency between cpu-z, cpu-z is right.
The best for know multiplier is to make a RDMSR, but my driver don't provide it.

[necron66]

Minor error there.
Problem has been there for some time. But who cares

Read what I said "its prolly nothing", and like I said I didn't notice it on XP, only since I use Vista, which is from hmmmm, the day I made that post.....

->necron66: if you find a difference in memset reading frequency between cpu-z, cpu-z is right.
The best for know multiplier is to make a RDMSR, but my driver don't provide it.

No worries mate