AMD Cayman info (or rumor)

[Dimitriman]

doesnt anyne else find this 32 rops number too low?

[-Sweeper_]

doesnt anyne else find this 32 rops number too low?

me.. I hope it doesnt hold back cayman.

at least 2Gb framebuffer is confirmed

[kadozer]

me.. I hope it doesnt hold back cayman.

at least 2Gb framebuffer is confirmed

Hope this is for 6950. They didn't wanna show their cards on that slide listing only the Power for both.

[blindbox]

VLIW4

New architecture anyone?

Anyone has the original source (says there expreview on all 3 photos).

By the way, there is absolutely no indication of how big Cayman is on that photo, in case someone is claiming "THAT CHIP IS HUGE!!one".

[Pantsu]

Looks almost as big as a GF100. If AMD can keep up their perf/mm^2 this thing will surpass GTX 580 easily.

[informal]

If this thing is indeed VLIW4 and has 1920SP,it's game over for any GF1xx chip,no matter if it has full 512 CUDA cores and high clock. With Cayman XT on the market,Cypress is going to be lowered in mid-high class and GTX480 as well.Antilles will be uber high end,in a class of its own,in line with Chuck Norris comments we already saw.

[kadozer]

If this thing is indeed VLIW4 and has 1920SP,it's game over for any GF1xx chip,no matter if it has full 512 CUDA cores and high clock. With Cayman XT on the market,Cypress is going to be lowered in mid-high class and GTX480 as well.Antilles will be uber high end,in a class of its own,in line with Chuck Norris comments we already saw.

Can you educate or expand on VLIW4 I'm not familiar with this.

[spursindonesia]

The box shape in the middle of the PCB isn't the chip itself, but the substrate/packaging size with its corresponding pin out. The chip itself would be rotated 45 degree in orientation, just like Cypress and Bart, and if you look further behind, R600. I still believe the chip won't be bigger than 400 mm^2, with TDP no higher than 230 w.

[Pantsu]

Yeah now that I look the pcb doesn't seem that much longer than a 6870.

Rop count seems a bit low, but who knows how it works with the VLIW4 architecture. 2 GB reference is nice though.

[Funky]

8 phase power on stock pcb. yum!

[nascasho]

Whooa, looks sweet!

So educate me on what VLIW4 is...

[ohnoitseddy]

Do you remember all the 4D instead of 5D shader rumors for the HD68xx? If I'm not mistaken, it's that. Charlie wrote a bit on it here:

http://www.semiaccurate.com/2010/09/...thern-islands/

But, as we already know, it didn't turn out true for the HD68xx cards.

[ajaidev]

For people who dont know AMD used 5 way design's for most of the cards till now including the 68xx now VLIW4 is different in several ways.

The easiest way to tell the difference is that VLIW4 is suppose to use 4 medium sized units where as the old 5 way design used 1 big and 4 small units.

[Macadamia]

^ Evergreen had OCP so Furmark didn't use more than board power.

WXYZT turns to WXYZ with T probably done in emulation (WXYZ or T for GPGPU).
The penultimate reason for this is die size. And yet Cayman is still big. Makes you wonder.

[Solus Corvus]

^ Evergreen had OCP so Furmark didn't use more than board power.

WXYZT turns to WXYZ with T probably done in emulation (WXYZ or T for GPGPU).
The penultimate reason for this is die size. And yet Cayman is still big. Makes you wonder.

I disagree about die space. Reducing the width of the SP increases the ratio of logic per SPU. Without knowing more specific architectural details I'd guess 5D->4D is ambiguous or detrimental to die space.

[Macadamia]

I disagree about die space. Reducing the width of the SP increases the ratio of logic per SPU. Without knowing more specific architectural details I'd guess 5D->4D is ambiguous or detrimental to die space.

Hm? How does logic go up? Logic should go down (minorly, 10-15% die size would be fortunate) and perf-logic ratio should get boosted just slightly less.

Unless it's WT-XT-YT-ZT which might be what you mean. That'd be quite an increase actually, but the ratio's way overdone.

I'm thinking of WXYZ + logic in the SIMD blocks that allows transcendentals to be performed through looping or such.

[Solus Corvus]

Iirc to take advantage of all the the SPUs per SP certain scheduling conditions have to be met that makes it very difficult to even get close to the theoretical max performance with real world code

Which might be exactly the reason for a change from 5D. Theoretical power going unused only drags down energy efficiency. Higher real utilization of units will increase overall power usage, but will also increase performance/watt - maybe to a greater proportion.

What about low ROPs listed? Wouldn't that still be a bottleneck?

Maybe, but we don't know if they are directly comparable to current rops anyway.

Hm? How does logic go up? Logic should go down (minorly, 10-15% die size would be fortunate) and perf-logic ratio should get boosted just slightly less.

Unless it's WT-XT-YT-ZT which might be what you mean. That'd be quite an increase actually, but the ratio's way overdone.

I'm thinking of WXYZ + logic in the SIMD blocks that allows transcendentals to be performed through looping or such.

First off we are assuming that they didn't increase the size of the register file, complexity of the branch predictor, size of the texture units, size of the L1 cache, amount of shared memory, and complexity of the controlling logic - if they did then every SP and SIMD would have an increased ratio of logic to SPUs. Even if they kept it the same we are talking about 25% more SPs for the same number of SPUs (400 SPs vs 320 SPs). But they seem to be increasing the SPU count to 1920 if the rumors are true. So that's a 50% increase in the number of SPs (480 SPs vs 320 SPs). And if 16 SPs per SIMD is the same then it will be a 50% increase in texture units, L1 cache, shared memory, and controlling logic (30 SIMDs vs 20 SIMDs).

This may be a very powerful chip.

[Aten-Ra]

Can we have 32 SPs per SIMD with 4 Texture Units ??

Something like 16x2 SPs with 4-way VLIW 128 Shaders with 4 Texture Units

[Gipsel]

Hm? How does logic go up? Logic should go down (minorly, 10-15% die size would be fortunate) and perf-logic ratio should get boosted just slightly less.

That ~10-15% number was also my estimate. It's of course dependent on the actual code running. It will be possible to construct cases were Cayman will be slower than Cypress (if Cayman doesn't have significantly more than 1920 SPs). But generally, it will gain the most in situations where the VLIW5 architecture fared worst in comparison to nvidia.

Unless it's WT-XT-YT-ZT which might be what you mean. That'd be quite an increase actually, but the ratio's way overdone.

I'm thinking of WXYZ + logic in the SIMD blocks that allows transcendentals to be performed through looping or such.

Actually it is already known how the VLIW4 units will be organized. The codepath for that arch in the driver is functional since Catalyst 10.4, I've posted some stuff about that over at B3D 10 days ago.

The transcendental functions are done by the xyz units working together (just like it is done for double precision already now, only that it takes 3 slots), so 3 of the 4 slots of the VLIW unit are used to calculate a transcendental. The fourth slot (w) does not take part in that and is still free to use in the same cycle. That means a good part of the t unit got split up in three parts and is distributed to the x, y and z units.
Another function of the t unit was doing format conversions and roundings. This functionality got replicated to all subunits. That means for this kind of stuff Cayman will fly.
24bit integer arithmetics are now fully supported by Cayman and can be done in all 4 slots (Evergreen had only partial support which was not really used).
A 32Bit integer multiplication will unfortunately block all 4 slots (could be done by the t unit with the xyzw slots free for use by other instructions in Evergreen), but this is probably the price to pay to get some transistor savings from the change.
All other integer instructions can again be done in all 4 slots (as before).

Double precision instructions behave the same way as in Cypress. Everything involving a multiplication (MUL, FMA) takes 4 slots while the other stuff (like ADD and conversions) takes 2 slots. That means the DP:SP ratio is 1:4.

[blindbox]

That ~10-15% number was also my estimate. It's of course dependent on the actual code running. It will be possible to construct cases were Cayman will be slower than Cypress (if Cayman doesn't have significantly more than 1920 SPs). But generally, it will gain the most in situations where the VLIW5 architecture fared worst in comparison to nvidia.

Actually it is already known how the VLIW4 units will be organized. The codepath for that arch in the driver is functional since Catalyst 10.4, I've posted some stuff about that over at B3D 10 days ago.

The transcendental functions are done by the xyz units working together (just like it is done for double precision already now, only that it takes 3 slots), so 3 of the 4 slots of the VLIW unit are used to calculate a transcendental. The fourth slot (w) does not take part in that and is still free to use in the same cycle. That means a good part of the t unit got split up in three parts and is distributed to the x, y and z units.
Another function of the t unit was doing format conversions and roundings. This functionality got replicated to all subunits. That means for this kind of stuff Cayman will fly.
24bit integer arithmetics are now fully supported by Cayman and can be done in all 4 slots (Evergreen had only partial support which was not really used).
A 32Bit integer multiplication will unfortunately block all 4 slots (could be done by the t unit with the xyzw slots free for use by other instructions in Evergreen), but this is probably the price to pay to get some transistor savings from the change.
All other integer instructions can again be done in all 4 slots (as before).

Double precision instructions behave the same way as in Cypress. Everything involving a multiplication (MUL, FMA) takes 4 slots while the other stuff (like ADD and conversions) takes 2 slots. That means the DP:SP ratio is 1:4.

I just realized that's your first post ! Yet a good one!

[informal]

Effectively,Cayman could have 50% more SP resources than Cypress,taking into account the grouping per SIMD. If the clocks stay in the range of Cypress,this thing will be the fastest single GPU card on the market,hands down. Now,how will they manage to put two of those monster for Antilles card and keep "reasonable" TDP is another question.

[ajaidev]

Effectively,Cayman could have 50% more SP resources than Cypress,taking into account the grouping per SIMD. If the clocks stay in the range of Cypress,this thing will be the fastest single GPU card on the market,hands down. Now,how will they manage to put two of those monster for Antilles card and keep "reasonable" TDP is another question.

There are three possible ways to do that:

1. Decrease clock
2. Decrease number of SIMD
3. Using a new spin of the silicon with other enhancements/modifications.

Since cayman is a 4 way design i would think so will Antilles...

[Mad Pistol]

There are three possible ways to do that:

1. Decrease clock
2. Decrease number of SIMD
3. Using a new spin of the silicon with other enhancements/modifications.

Since cayman is a 4 way design i would think so will Antilles...

What I would like to see is an implimentation of AMD's "Turbo Core" on their dual GPU solutions. What this would mean for cards like Antilles is that on games that can use more than one GPU, the chips would clock down slightly and run in Crossfire configuration. However, in games that DON'T have a Crossfire profile or aren't optimized to run on multi-GPU solutions, one of the cores would overclock to the full speed of a Cayman XT card and run on only one GPU core while the other GPU core is essentially turned off.


This would be an intelligent solution much like the Turbo-mode that intel implements on their i3/i5/i7 CPU's, only it would apply to GPU's. This would also allow them to intelligently keep Antilles within the 300 watt PCIe spec while in dual-GPU mode and it would allow the card to perform very well on games that only utilize one GPU. They've already got the technology implemented in their cards (notice the 17watts of power consumption at idle). Now they just need to expand upon it and add intelligent power gating to the mix. It could probably be done via software.

That would be a win-win design. However, it's probably wishful thinking to hope for something like that.

[kadozer]

In Cypress (and back to R600) there were 5 SPUs (Stream Processing Units) per SP (Streaming Processor).
Like in the first image here: http://www.anandtech.com/show/2841/4
Now there will be 4 SPUs per SP. And as ajaidev points out, there may be a different arrangement of simple and complex units within the SP instead of 4+1.

If they keep a grouping of 16 SPs per SIMD, and there are 1920 SPUs, then Cayman will have 30 SIMDs per chip.

The reason for such a change might be to increase utilization. It could have good results if one or two of the units in your 5 wide design are usually sitting idle. That's why RV770 and Evergreen had such a huge difference between low utilization (games) and high utilization (furmark) in terms of power-draw and heat output.


They have had a 5-wide design for a while now. Why assume that's never going to change? Especially on a generational change?

Effectively,Cayman could have 50% more SP resources than Cypress,taking into account the grouping per SIMD. If the clocks stay in the range of Cypress,this thing will be the fastest single GPU card on the market,hands down. Now,how will they manage to put two of those monster for Antilles card and keep "reasonable" TDP is another question.

What about low ROPs listed? Wouldn't that still be a bottleneck?

[BrowncoatGR]

If it is indeed a 4 port VLIW architecture this will be very expensive for AMD as i speculate they will have to recoup the R&D costs for moving the SI design from it's initial 28nm target to 40nm using just one derivative. This of course will allow them to finalize the design on a well known process before they move it to the murky waters of 28nm and therefore lower risk. I suspect we will see a 5770 replacement as a 28nm test vehicle as soon as the process is ready for production.

In Cypress (and back to R600) there were 5 SPUs (Stream Processing Units) per SP (Streaming Processor).
Like in the first image here: http://www.anandtech.com/show/2841/4
Now there will be 4 SPUs per SP. And as ajaidev points out, there may be a different arrangement of simple and complex units within the SP instead of 4+1.

If they keep a grouping of 16 SPs per SIMD, and there are 1920 SPUs, then Cayman will have 30 SIMDs per chip.

The reason for such a change might be to increase utilization. It could have good results if one or two of the units in your 5 wide design are usually sitting idle. That's why RV770 and Evergreen had such a huge difference between low utilization (games) and high utilization (furmark) in terms of power-draw and heat output.


They have had a 5-wide design for a while now. Why assume that's never going to change? Especially on a generational change?

Iirc to take advantage of all the the SPUs per SP certain scheduling conditions have to be met that makes it very difficult to even get close to the theoretical max performance with real world code