M3A overclocking

[jpierce555]

Due to the chipset or do you expect no suitable bios here also.
My phenom failed prime95 at 210x11 last night, so switched back to my old m2a-vm and voila the system requires less power in idle (no CnQ) now.

When Asus gave me the email address to the engineering department they also stated they don't support overclocking, so in a word yes I don't expect a suitable bios.

[SocketMan]

Under "storage" in bios it gives options of:
1.Enable/disable The SATA chip
2.When enabled you can toggle the "function" IDE/RAID/AHCI
3.I tried AHCI first and it gave me some problems,then it turns out it's made by Intel,so I switched to "RAID" right away
Then made the floppy of the Asus Support CD and used it during install.

4.My SATA DVD only works when the SATA "function" set to IDE, but then you loose the RAID
So as far as I know you can't have raid and SATA DVD drive at the same time.

I ended up using a sata/ide to usb adapter- came in handy.

Then just swapped DVD drives later with my other machine (it had IDE DVD).

[Thesavage]

Under "storage" in bios it gives options of:
1.Enable/disable The SATA chip
2.When enabled you can toggle the "function" IDE/RAID/AHCI
3.I tried AHCI first and it gave me some problems,then it turns out it's made by Intel,so I switched to "RAID" right away
Then made the floppy of the Asus Support CD and used it during install.

4.My SATA DVD only works when the SATA "function" set to IDE, but then you loose the RAID
So as far as I know you can't have raid and SATA DVD drive at the same time.

I ended up using a sata/ide to usb adapter- came in handy.

Then just swapped DVD drives later with my other machine (it had IDE DVD).

My raid and sata run perfectly off the "raid" option in the bios no problem on both the m3a and m3a32 deluxe

[crazydiamond]

hey socketman, i see your runnin raid on the m3a too. do you know if there is a way to not have the SATA dvdrw being seen as a raid dvd drive? in my boot priority it shows regular dvd drive and a raid dvd drive, just curious if this is how its gonna be or if i can change that. also, on the 'press ctrl f' screen (after asus splash screen) it shows my 2 hd's in raid by #1 and right under that it shows #4 raid dvd drive and that one is blinking. is there a way to bypass this screen or something?

and finally, my last build was pretty much the same except for the last one was running on 1 hard drive. i was getting boot times about 25 seconds and now on a fresh install with this raid0 its taking like 40-45 seconds. im going to run some benchies on my HD's tonight. im getting same superpi 1m scores as my last rig so performance wise its about the same, its just bootup takes much longer. any ideas?

heres the hardware:
asus m3a
x2 5000+ be
4x1gb ballistix
evga 8800gt
2x320gb 7200.10 16mb raid 0
lite-on dvdrw
xclio 500w greatpower psu

[KTE]

Plus 1.55V-ish on cool good air will damage/degrade/kill the chip unless with cold.

[jpierce555]

I went to buy some thermal adhesive today and found the Gigabyte 790fx on a good sale and thought what the heck. Now I have to sell an old sempron/mobo, the KA3, the M3A, and one of my processors or else!

[jpierce555]

Sorry to derail the M3A side of this:

I just ran science mark on the Gigabyte 790fx with the Phenom stock and got the same score I got with the M3A turned up to its max, I consider that a really good start. It has voltage up to 1.38v for the cpu. The bios looks more familiar. It has its own oc software, good thing AOD crashes on it. Interesting is Windows does not realize the difference, I did not have to re-activate. It was a very easy install. The layout fits my case much better, still a little clearance issue with the nb and the Infinity hs. I also see that the SATA cable attachments are in a bad place. A major plus is all of the fan sockets.

I will be back tomorrow to let you know if I can oc this board or not.

[RebelsHaven]

Hmmm... may be a little confusion here... When you say it's "set", you mean it's a "1" correct? I'm already writing a 1b to the 4th bit of the MSRC001_0015 register. If the BIOS already has written a 1b, of course, there will be no change. Do you want a 0b written to the 4th bit or a 1b? I'm writing a 1b. Very easy to change. Here's a BIOS with it the other way:

http://www.lejabeach.com/ASUS/M3A/601RHCF3.zip

This BIOS is UNTESTED and the BIOS chip is soldered in. If the BIOS is corrupt, RMA may be the only answer! Be careful!

[justapost]

Hmmm... may be a little confusion here... When you say it's "set", you mean it's a "1" correct? I'm already writing a 1b to the 4th bit of the MSRC001_0015 register. If the BIOS already has written a 1b, of course, there will be no change. Do you want a 0b written to the 4th bit or a 1b? I'm writing a 1b. Very easy to change. Here's a BIOS with it the other way:

http://www.lejabeach.com/ASUS/M3A/601RHCF3.zip

This BIOS is UNTESTED and the BIOS chip is soldered in. If the BIOS is corrupt, RMA may be the only answer! Be careful!

Hi Polygon,

Yepp the bit must be unset, that reenables the TLB.
Tried the new bios and it works. But you remove that bit only on core0. It should be done on all four cores, but that may cause problems if cores are disabled via the bios.

Anyway, thank you for your effort, having an option for the tlb-fix is a comfortable thing.

[RebelsHaven]

Hello!
Interesting. That same fix sets or unsets all 4 cores in the Biostar TA770 board. There are several MSR's that there is only 1 per CPU. Isn't the HWCR one of the MSR's that are 1 per CPU and not in every core?

[justapost]

Hello!
Interesting. That same fix sets or unsets all 4 cores in the Biostar TA770 board. There are several MSR's that there is only 1 per CPU. Isn't the HWCR one of the MSR's that are 1 per CPU and not in every core?

I ran RightMark multi-threaded mem test and it gave me the same bandwidth on all cores.
Guess you are right about the HWCR. But it's odd that CrystalCPU still reads 8h for cpu's 1-3 but 0h for cpu0. If it's the same register for all cores it should read the same value, or is only the core0 register used in a per cpu case?

[RebelsHaven]

I honestly don't know if it's 1 per CPU or 1 per core. I assumed 1 per CPU because setting it on core0 shows it changed on the other 3 in the Biostar board. I'm not sure how to address the other cores from the BIOS anyhow.

The BKDG for the Phenom is very tough to read and many things are not explained, where in the BKDG for AM2 and A64, it was very clear...

But, I'm glad it seems to be working correctly... Thanks for testing it!

[justapost]

I honestly don't know if it's 1 per CPU or 1 per core. I assumed 1 per CPU because setting it on core0 shows it changed on the other 3 in the Biostar board. I'm not sure how to address the other cores from the BIOS anyhow.

Only if you change it from within the bios or does it also behave like this if you change that register with crystalcpu?

The BKDG for the Phenom is very tough to read and many things are not explained, where in the BKDG for AM2 and A64, it was very clear...

Dunno the guide for A64/AM2 but the BKDG really is tough, hope a new revision will add abit extra background information.

But, I'm glad it seems to be working correctly... Thanks for testing it!

Glad I could help.

BTW: A you aware of an 770 chipset mobo, whom is able to apply more than 1,25V to a k10 cpu?

[RebelsHaven]

Writing the Biostar from the BIOS, changes all 4 cores for the TBL-Fix only. Writing to the other patch you discovered(MSRC001_1023), does not write to all 4 cores. Also writing to P-State0(MSRC001_0064) only writes to P-State0 for core0... I can't figure out how to write to all 4 cores!

Writing to MSRC0010015 with CrystalCPUID only changes 1 at a time...

I've had the Biostar TA770-A2+ running with 1.5Vcore for my Phenom....

I'm getting the ASUS M3A and if it needs a Vcore mod, I can do that, no problem. Is that Vcore limited?

[justapost]

Writing the Biostar from the BIOS, changes all 4 cores for the TBL-Fix only. Writing to the other patch you discovered(MSRC001_1023), does not write to all 4 cores. Also writing to P-State0(MSRC001_0064) only writes to P-State0 for core0... I can't figure out how to write to all 4 cores!

I took a look in the linux kernel sources. The function whom is affected by the linux-tlb patch gets called for core0 only. I'll inspect the msr registers in linux now.

I've had the Biostar TA770-A2+ running with 1.5Vcore for my Phenom....

I'm getting the ASUS M3A and if it needs a Vcore mod, I can do that, no problem. Is that Vcore limited?

My theory for the M3A is that those fields labled prozessor and nb voltages are the cpu/nb vid's. I can select more than 1,25V but the internal decimal places get mapped to the 1,2V-1,25V range.
AMD Power Monitor reports exact the values i set in the bios, cpu-z's vcore is pretty close 1,264V max if I select 1,25V in the bios.
You have an BE or an 9500/9600 as those have upward locked vid's?

[justapost]

I took a look in the linux kernel sources. The function whom is affected by the linux-tlb patch gets called for core0 only. I'll inspect the msr registers in linux now.

The registers all showed the modified value. The patch adds a note to the kernel log if it changes the msr registers.

Here is the excerpt of the log for cores 1-3, core 0 get's called on an earlier stage.

SMP alternatives: switching to SMP code
Booting processor 1/4 APIC 0x1
Initializing CPU#1
Calibrating delay using timer specific routine.. 4400.40 BogoMIPS (lpj=8800810)
CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
CPU: L2 Cache: 512K (64 bytes/line)
CPU 1/1 -> Node 0
AMD erratum 298 bios fix disabled
CPU: Physical Processor ID: 0
CPU: Processor Core ID: 1
AMD Phenom(tm) 9500 Quad-Core Processor stepping 02
SMP alternatives: switching to SMP code
Booting processor 2/4 APIC 0x2
Initializing CPU#2
Calibrating delay using timer specific routine.. 4400.39 BogoMIPS (lpj=8800788)
CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
CPU: L2 Cache: 512K (64 bytes/line)
CPU 2/2 -> Node 0
AMD erratum 298 bios fix disabled
CPU: Physical Processor ID: 0
CPU: Processor Core ID: 2
AMD Phenom(tm) 9500 Quad-Core Processor stepping 02
SMP alternatives: switching to SMP code
Booting processor 3/4 APIC 0x3
Initializing CPU#3
Calibrating delay using timer specific routine.. 4400.45 BogoMIPS (lpj=8800903)
CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
CPU: L2 Cache: 512K (64 bytes/line)
CPU 3/3 -> Node 0
AMD erratum 298 bios fix disabled
CPU: Physical Processor ID: 0
CPU: Processor Core ID: 3
AMD Phenom(tm) 9500 Quad-Core Processor stepping 02
Brought up 4 CPUs

You can see the patch get's applied for each core in opposite to my first adoption.
Aint there no simple assembler commando to select the cpu? Don't know much about bios coding, I assumed you change the jump target in the gui part of the bios to a place where you have stored your modified machine code.

[RebelsHaven]

Aint there no simple assembler commando to select the cpu? Don't know much about bios coding, I assumed you change the jump target in the gui part of the bios to a place where you have stored your modified machine code.

In x86 assembly, there is no directive that I know of to select a different core. I'm afraid it might have to be performed with a call to a seperate module. I really don't know... But I think the other 3 cores may get addressed by APIC directives...

To do the mod I did, I wrote a substitute PCI LAN Boot ROM and replaced the original. The new ROM writes to the MSR when it's executed and that is when the LAN Boot is enabled during POST....

[justapost]

In x86 assembly, there is no directive that I know of to select a different core. I'm afraid it might have to be performed with a call to a seperate module. I really don't know...

Last time I wrote assemble code was more than twenty years ago on an atari st, so i'm not up to date here. I'll swap disc again and try to find out how it is done in the linux kernel.

To do the mod I did, I wrote a substitute PCI LAN Boot ROM and replaced the original. The new ROM writes to the MSR when it's executed and that is when the LAN Boot is enabled during POST....

That sounds like a pretty save way to mod the bios. Is this A64 Rom Patcher public available? Googled for it but the only related result was your post here.

[RebelsHaven]

I have a 9500. I'll have to measure the Vcore at 1.50V to see what it is...

[KTE]

VID decides VCore on AM2+.

Achim: Check MSR C001_0064 and post this back please:




Tell me what you set in BIOS for CPU voltages and what CPUZ reads too.

[justapost]

VID decides VCore on AM2+.

Achim: Check MSR C001_0064 and post this back please:




Tell me what you set in BIOS for CPU voltages and what CPUZ reads too.

Aight, here we go.

PState-0 Status

COFVID Status


Results in 11010b for the vid equals 1,225V That's what I set in the bios as prozessor voltage.
CPU-Z 1,216V/idle 1,232V/load.

How much higher can vcore be choosen than the vid on your mobo?

[KTE]

Aight, here we go.

PState-0 Status

COFVID Status


Results in 11010b for the vid equals 1,225V That's what I set in the bios as prozessor voltage.
CPU-Z 1,216V/idle 1,232V/load.

Those are stock VID/VCore on 9500, yep. VID is locked on 9500/9600. Max voltage on 1.25VID is around 1.488V on AM2+ CPU.

What happens if you change the processor voltage in BIOS, do those bit values change?

How much higher can vcore be choosen than the vid on your mobo?

See above. Differs for each VID for unlocked version though.

[RebelsHaven]

Thanks, did not expect that much info.

Yes, there is a lot to it...

Vcore check:
Biostar TA770 A2+
Set Vcore: +.225V above default.
BIOS Reads: 1.47V
DMM Reads: 1.493V

[justapost]

Yes, there is a lot to it...

Vcore check:
Biostar TA770 A2+
Set Vcore: +.225V above default.
BIOS Reads: 1.47V
DMM Reads: 1.493V

Thank you that sorts out my fear that it's an common chipset issue.

Made my way thru the linux source and found this function. She's used to call the cpu initalisation function whom applies the tlb-fix related stuff.

arch/x86/kernel/smp_64.c line 329

/*
 * this function sends a 'generic call function' IPI to all other CPU
 * of the system defined in the mask.
 */

static int
__smp_call_function_mask(cpumask_t mask,
			 void (*func)(void *), void *info,
			 int wait)
{
	struct call_data_struct data;
	cpumask_t allbutself;
	int cpus;

	allbutself = cpu_online_map;
	cpu_clear(smp_processor_id(), allbutself);

	cpus_and(mask, mask, allbutself);
	cpus = cpus_weight(mask);

	if (!cpus)
		return 0;

	data.func = func;
	data.info = info;
	atomic_set(&data.started, 0);
	data.wait = wait;
	if (wait)
		atomic_set(&data.finished, 0);

	call_data = &data;
	wmb();

	/* Send a message to other CPUs */
	if (cpus_equal(mask, allbutself))
		send_IPI_allbutself(CALL_FUNCTION_VECTOR);
	else
		send_IPI_mask(mask, CALL_FUNCTION_VECTOR);

	/* Wait for response */
	while (atomic_read(&data.started) != cpus)
		cpu_relax();

	if (!wait)
		return 0;

	while (atomic_read(&data.finished) != cpus)
		cpu_relax();

	return 0;
}

Seems it's done true IPI (Inter Prozessor Interrupts).

The involved functions seem to solve that true APIC register modification.
APIC inline functions are defined in include/asm/apic.h.

[RebelsHaven]

OK, thanks! Inter-Processor Interrupts was one of my suspicions...