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Have learned some about Zen 2's quirks tonight...probably should have picked one of these up a long time ago.
PBO is not useless but with some settings it seems useless / will perform worse than stock, especially when set too high. It appears there are limits in AGESA/SMU regardless of what is actually set with PBO to protect the chip from exploding.
The SMU / FIT will only ever allow it to hit ideal TDC/EDC/PPT numbers and certain settings skew it slightly worse even if not tanking it, so it takes lots of testing, combined with offset undervolt.
PBO Scalar actually does something, but raises the Core VID to unsafe voltages (1.41-1.45v+ all core) past ~4x, but can be mitigated with heavy offset undervolt, increasing MT performance significantly but at the risk of unstable ST due to max VID the chip ever chooses being 1.475-1.50v = low actual ST voltage. Had a hard time booting to windows or even posting with too much undervolt or combination of undervolt and PBO settings the SMU didn't like, - ie. Auto OC @ -0.125v offset and +75 MHz fine, but even -0.05v offset and +100, or +150 still completely unstable...or set PPT to 200w+ after -0.125v undervolt and also unstable, it is changing something with single core / light load boost aggressiveness and breaking everything.
More vdroop with PBO is better, any LLC is bad - it's possible to push to the limit of stability if undervolted as much as possible with PBO using a high scalar number, the chip will just keep going for roughly the same TDC/EDC/PPT targets and adjust it's MT Core VID to the moon.
All core OC basically useless, CCX OC not as useless, but depends how ballsy you want to be with voltage and what you are doing - CCX OC is okay if just gaming / no heavy all core loads. Example this CPU does 4.3 all core or 4.45/4.3 CCX OC @ 1.31v load - this is too high voltage for P95 Small FFT but fine for almost everything else (Blend/Cinebench/AIDA stress loop forever, etc.) but hits 75-85c on 360mm AIO in those. 4.4/4.25 can be had at 1.27v actual.
CPPC on, started at TDC 300a/EDC 300a/PPT 300w Scalar 10x, -0.05v undervolt, worked down in 20a/20a/20w increments until I gained a little more performance at TDC 180a/EDC 180a/PPT 180w.
P95 FFT 128k after 2 minutes
1.38v VID 1.23v actual - temp 75c
Clock - 3975
TDC - 121a
EDC - 157a
PPT - 173w (this was lower ~165-170w @ 200-280w PPT set)
Continued undervolting with P95 128K FFT running using ASUS AI Suite until I lost a worker thread in P95 @ -0.1375v...settled on -0.125v.
PBO TDC 180a/EDC 180a/PPT 180w, Scalar 10x, -0.125v offset, Auto OC +75MHz
P95 FFT 128K
1.41v VID 1.2v actual - temp 76c
Clock - 4100
TDC - 121a
EDC - 156a
PPT - 173w
CB R20
1.45v VID 1.25v actual - temp 68c
Clock - 4150
TDC - 95a
EDC - 161a
PPT - 150w
PBO TDC 130a/EDC 170a/PPT 180w, Scalar 10x, -0.125v offset, Auto OC +75MHz
P95 FFT 128k
1.41v VID 1.2v actual - temp 76c
Clock - 4100
TDC - 119a
EDC - 157a
PPT - 174w
CB R20 - 7433 score
1.45v VID 1.25v actual - temp 68c
Clock - 4175
TDC - 97a
EDC - 163a
PPT - 154w
PBO - TDC 130a/EDC 160a/PPT 180w, Scalar 10x, -0.125v offset, Auto OC +75MHz
P95 FFT 128k
1.4v VID 1.19v actual - temp 75c
Clock - 4100
TDC - 116a
EDC - 153a
PPT - 168w
CB R20 - 7497 score
1.44-1.45v VID 1.24-1.25v actual - temp 66c
Clock - 4200
TDC - 96a
EDC - 160a (capped)
PPT - 153w
CB R20 ST - score 527
Clock - 4500-4600 - temp 50c
1.469-1.5v VID, 1.35-1.375v actual
PPT - 45w
I've now seen peak ST frequency of 4650 with these settings as well outside of R20.
My max scores in R20 -
7867 MT / 518 ST with CCX OC @ 4450/4300 1.306v actual
7497 MT (-4.7%) / 527 (+1.7%) @ 4200 MT 1.25v actual and 4500-4600 ST 1.35-1.375v actual.
The PBO boost is even better with lighter loads ... only ~50-100 MHz off from manual CCX OC. Considering my temps are much lower and the chip will probably degrade less this way, I think I'll stay with PBO and -0.125v w/ 10x scalar.
12-thread CB20 = 4250 1.28v actual
8-thread CB20 = 4300-4325 1.3v actual
6-thread CB20 = 4300-4425 1.32v actual
4-thread CB20 = 4400-4450 1.34v actual

Something to note in this screenshot is the power reporting deviation - the PPT number is not correct under load, but the since the SMU is always hunting for a similar max, these PBO settings happen to skew the power reporting deviation even more than usual resulting in the higher boosting behavior with PBO and the ridiculous VIDs that would be nearing 1.35v actual voltage all core with no offset. With these settings + the voltage offset, the CPU is always sitting higher up in the AVFS curve than it should be, at a lower actual voltage than expected, while being told it is sucking less power from the VRM than actual.
Last edited by BeepBeep2; 12-22-2020 at 12:37 AM.
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