tRRD 4 is real min internally in the chipset. Remember, bus is 64 bit wide. Can't send ACT before last burst of 4 clocks is complete. Setting lower register will just revert to min or arbitrary value.
tRRD 4 is real min internally in the chipset. Remember, bus is 64 bit wide. Can't send ACT before last burst of 4 clocks is complete. Setting lower register will just revert to min or arbitrary value.
Last edited by Raja@ASUS; 06-28-2013 at 05:52 AM.
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