AMD "Steamroller/Excavator" -info, speculations and experience

[G.Foyle]

Good find Flanker and nice analysis informal

Increase dispatch bandwidth to 8 INT ops per cycle (4 to each core), from 4 INT ops per cycle (4 to just 1 core). 4 ops per cycle per core remains unchanged. <-massive improvement in MT workload

Looks to me more like extracting additional inctruction-level parallelism, not thread-level parallelism.

Change from 4 to 3 FP pipe stages. <- don't know what to think of this. It's listed as improvement so less stages is good(shorter pipeline usually means better IPC).

Lower latency means same max theoretical IPC, but lower branch misprediction penalty, less waiting for the result of previous operations - should be a nice increase in real-world apps. Also this seems unusual - so far most architectures evolved from shorter to longer pipeline, not the other way.

About the memory controllers: I hope the MC can work in both modes (DDR3 and GDDR5) and selects one mode at boot, similar to how Deneb had DDR2/DDR3 controller. Another possibility is selecting modes during packaging (blowing on-chip fuses), in which case SKUs will be locked to one or other type of memory, probably GDDR5 for mobile and ULV chips and DDR3 for desktop. I hope it's the previous, but the latter seems more likely.