Lol, that will teach me for only hanging around in the storage section.

The X25-M G1 used 50nm NAND and Intel claimed a write amplification factor of 1.1. The best possible is 1, so from 2008 when the X25-M G1 came out there has been near zero scope for improvement in f/w algorithms to further reduce WA.

The only way to get below 1 is to use compression. To get closer to 1 the only other option is to use DRAM to optimise how writes are placed on the NAND.

Looking at it that way it makes more sense to me now why Intel have switched to SF and why drives with no compression are having to start to use large DRAM caches to offset reduced P/E cycles (which Intel have always avoided).

It could be that drives with large DRAM caches are negatively impacted by the sustained writes that occur in the endurance workload as opposed to normal workloads that occur in real life. That does not explain the V3 or Octane however.